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Searched refs:DM_PP_MAX_CLOCK_LEVELS (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/display/dc/
Ddm_services_types.h95 #define DM_PP_MAX_CLOCK_LEVELS 16 macro
99 uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
109 struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS];
119 struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS];
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c221 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels()
225 DM_PP_MAX_CLOCK_LEVELS); in pp_to_dc_clock_levels()
227 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels()
247 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels_with_latency()
251 DM_PP_MAX_CLOCK_LEVELS); in pp_to_dc_clock_levels_with_latency()
253 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels_with_latency()
274 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { in pp_to_dc_clock_levels_with_voltage()
278 DM_PP_MAX_CLOCK_LEVELS); in pp_to_dc_clock_levels_with_voltage()
280 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; in pp_to_dc_clock_levels_with_voltage()