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Searched refs:DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_intel_display.c170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
Dpsb_intel_reg.h237 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ macro
/drivers/gpu/drm/i915/display/
Dintel_dpll.c838 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
1027 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
Dintel_display.c6596 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
/drivers/gpu/drm/i915/
Di915_reg.h3503 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ macro