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Searched refs:ENGINE_WRITE (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dgen6_engine_cs.c426 ENGINE_WRITE(engine, RING_IMR, in gen6_irq_enable()
437 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen6_irq_disable()
443 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); in hsw_irq_enable_vecs()
453 ENGINE_WRITE(engine, RING_IMR, ~0); in hsw_irq_disable_vecs()
Dintel_execlists_submission.c2466 ENGINE_WRITE(engine, RING_EMR, ~0u); in execlists_irq_handler()
2467 ENGINE_WRITE(engine, RING_EIR, eir); in execlists_irq_handler()
2744 ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR, in reset_csb_pointers()
2767 ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR, in reset_csb_pointers()
2818 ENGINE_WRITE(engine, RING_EMR, ~0u); in enable_error_interrupt()
2819 ENGINE_WRITE(engine, RING_EIR, ~0u); /* clear all existing errors */ in enable_error_interrupt()
2853 ENGINE_WRITE(engine, RING_EMR, ~I915_ERROR_INSTRUCTION); in enable_error_interrupt()
3177 ENGINE_WRITE(engine, RING_IMR, in gen8_logical_ring_enable_irq()
3184 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen8_logical_ring_disable_irq()
Dintel_engine.h78 #define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__) macro
Dintel_ring_submission.c435 ENGINE_WRITE(request->engine, RING_TAIL, in i9xx_submit_request()
Dintel_engine_cs.c277 ENGINE_WRITE(engine, RING_HWSTAM, mask); in intel_engine_set_hwsp_writemask()