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Searched refs:FLD_VAL (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/bridge/
Dtc358764.c29 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
49 #define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */
50 #define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */
51 #define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */
52 #define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */
53 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */
58 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16)
59 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0)
61 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16)
62 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0)
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Dtc358775.c31 #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val) macro
125 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
126 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
162 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
163 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
164 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
165 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_wp.c139 l |= FLD_VAL(video_fmt->y_res, 31, 16); in hdmi_wp_video_config_format()
140 l |= FLD_VAL(video_fmt->x_res, 15, 0); in hdmi_wp_video_config_format()
170 timing_h |= FLD_VAL(timings->hbp, 31, 20); in hdmi_wp_video_config_timing()
171 timing_h |= FLD_VAL(timings->hfp, 19, 8); in hdmi_wp_video_config_timing()
172 timing_h |= FLD_VAL(timings->hsw, 7, 0); in hdmi_wp_video_config_timing()
175 timing_v |= FLD_VAL(timings->vbp, 31, 20); in hdmi_wp_video_config_timing()
176 timing_v |= FLD_VAL(timings->vfp, 19, 8); in hdmi_wp_video_config_timing()
177 timing_v |= FLD_VAL(timings->vsw, 7, 0); in hdmi_wp_video_config_timing()
Ddispc.c630 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) in dispc_ovl_set_scale_coef()
631 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) in dispc_ovl_set_scale_coef()
632 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) in dispc_ovl_set_scale_coef()
633 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); in dispc_ovl_set_scale_coef()
634 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) in dispc_ovl_set_scale_coef()
635 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) in dispc_ovl_set_scale_coef()
636 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) in dispc_ovl_set_scale_coef()
637 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); in dispc_ovl_set_scale_coef()
652 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) in dispc_ovl_set_scale_coef()
653 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); in dispc_ovl_set_scale_coef()
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Ddss.h60 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
63 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
Ddsi.c2221 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); in dsi_config_tx_fifo()
2254 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); in dsi_config_rx_fifo()
2670 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | in dsi_vc_write_long_header()
2671 FLD_VAL(ecc, 31, 24); in dsi_vc_write_long_header()
3688 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | in dsi_proto_timings()
3689 FLD_VAL(exit_hs_mode_lat, 15, 0); in dsi_proto_timings()
3943 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ in dsi_update_screen_dispc()
/drivers/gpu/drm/omapdrm/dss/
Dhdmi_wp.c138 l |= FLD_VAL(video_fmt->y_res, 31, 16); in hdmi_wp_video_config_format()
139 l |= FLD_VAL(video_fmt->x_res, 15, 0); in hdmi_wp_video_config_format()
181 timing_h |= FLD_VAL(vm->hback_porch, 31, 20); in hdmi_wp_video_config_timing()
182 timing_h |= FLD_VAL(vm->hfront_porch, 19, 8); in hdmi_wp_video_config_timing()
183 timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0); in hdmi_wp_video_config_timing()
186 timing_v |= FLD_VAL(vm->vback_porch, 31, 20); in hdmi_wp_video_config_timing()
187 timing_v |= FLD_VAL(vm->vfront_porch, 19, 8); in hdmi_wp_video_config_timing()
188 timing_v |= FLD_VAL(vm->vsync_len, 7, 0); in hdmi_wp_video_config_timing()
Ddispc.c819 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) in dispc_ovl_set_scale_coef()
820 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) in dispc_ovl_set_scale_coef()
821 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) in dispc_ovl_set_scale_coef()
822 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); in dispc_ovl_set_scale_coef()
823 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) in dispc_ovl_set_scale_coef()
824 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) in dispc_ovl_set_scale_coef()
825 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) in dispc_ovl_set_scale_coef()
826 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); in dispc_ovl_set_scale_coef()
841 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) in dispc_ovl_set_scale_coef()
842 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); in dispc_ovl_set_scale_coef()
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Ddss.h65 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
68 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
Ddsi.c1671 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); in dsi_config_tx_fifo()
1703 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); in dsi_config_rx_fifo()
2074 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | in dsi_vc_write_long_header()
2075 FLD_VAL(ecc, 31, 24); in dsi_vc_write_long_header()
2878 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | in dsi_proto_timings()
2879 FLD_VAL(exit_hs_mode_lat, 15, 0); in dsi_proto_timings()
3127 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ in dsi_update_screen_dispc()
/drivers/gpu/drm/tidss/
Dtidss_dispc.c375 static u32 FLD_VAL(u32 val, u32 start, u32 end) in FLD_VAL() function
387 return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); in FLD_MOD()
988 FLD_VAL(hsw - 1, 7, 0) | in dispc_vp_enable()
989 FLD_VAL(hfp - 1, 19, 8) | in dispc_vp_enable()
990 FLD_VAL(hbp - 1, 31, 20)); in dispc_vp_enable()
993 FLD_VAL(vsw - 1, 7, 0) | in dispc_vp_enable()
994 FLD_VAL(vfp, 19, 8) | in dispc_vp_enable()
995 FLD_VAL(vbp, 31, 20)); in dispc_vp_enable()
1018 FLD_VAL(align, 18, 18) | in dispc_vp_enable()
1019 FLD_VAL(onoff, 17, 17) | in dispc_vp_enable()
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/drivers/crypto/
Domap-aes.h25 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) macro
Domap-aes.c153 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); in omap_aes_write_ctrl()