Home
last modified time | relevance | path

Searched refs:HDMI_INFOFRAME_CONTROL0 (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Devergreen_hdmi.c415 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, in evergreen_hdmi_enable()
423 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, in evergreen_hdmi_enable()
432 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); in evergreen_hdmi_enable()
Drv770d.h707 #define HDMI_INFOFRAME_CONTROL0 0x7414 macro
Devergreend.h557 #define HDMI_INFOFRAME_CONTROL0 0x7044 macro
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.h72 SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
143 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
151 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
152 SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
675 uint32_t HDMI_INFOFRAME_CONTROL0; member
Ddce_stream_encoder.c654 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in dce110_stream_encoder_hdmi_set_stream_attribute()
768 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, in dce110_stream_encoder_update_hdmi_info_packets()
776 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, in dce110_stream_encoder_update_hdmi_info_packets()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1589 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); in dce_v6_0_audio_hdmi_enable()
1590 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); in dce_v6_0_audio_hdmi_enable()
1591 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in dce_v6_0_audio_hdmi_enable()
1592 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); in dce_v6_0_audio_hdmi_enable()
1604 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); in dce_v6_0_audio_hdmi_enable()
1605 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); in dce_v6_0_audio_hdmi_enable()
1606 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); in dce_v6_0_audio_hdmi_enable()
1607 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); in dce_v6_0_audio_hdmi_enable()
Ddce_v10_0.c1643 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in dce_v10_0_afmt_setmode()
1645 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); in dce_v10_0_afmt_setmode()
1727 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); in dce_v10_0_afmt_setmode()
1729 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); in dce_v10_0_afmt_setmode()
Ddce_v11_0.c1685 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in dce_v11_0_afmt_setmode()
1687 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); in dce_v11_0_afmt_setmode()
1769 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); in dce_v11_0_afmt_setmode()
1771 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); in dce_v11_0_afmt_setmode()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.h63 SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
152 uint32_t HDMI_INFOFRAME_CONTROL0; member
Ddcn10_stream_encoder.c597 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc1_stream_encoder_hdmi_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_stream_encoder.h65 SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
Ddcn30_dio_stream_encoder.c651 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc3_stream_encoder_hdmi_set_stream_attribute()