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Searched refs:I915_GTT_PAGE_SIZE (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/i915/selftests/
Di915_gem_evict.c56 I915_GTT_PAGE_SIZE); in populate_ggtt()
121 I915_GTT_PAGE_SIZE, 0, 0, in igt_evict_something()
136 I915_GTT_PAGE_SIZE, 0, 0, in igt_evict_something()
168 obj = i915_gem_object_create_internal(gt->i915, I915_GTT_PAGE_SIZE); in igt_overcommit()
245 .start = I915_GTT_PAGE_SIZE * 2, in igt_evict_for_cache_color()
246 .size = I915_GTT_PAGE_SIZE, in igt_evict_for_cache_color()
263 obj = i915_gem_object_create_internal(gt->i915, I915_GTT_PAGE_SIZE); in igt_evict_for_cache_color()
272 I915_GTT_PAGE_SIZE | flags); in igt_evict_for_cache_color()
279 obj = i915_gem_object_create_internal(gt->i915, I915_GTT_PAGE_SIZE); in igt_evict_for_cache_color()
289 (I915_GTT_PAGE_SIZE * 2) | flags); in igt_evict_for_cache_color()
Di915_gem_gtt.c114 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); in fake_dma_object()
700 obj = i915_gem_object_create_internal(vm->i915, 2 * I915_GTT_PAGE_SIZE); in pot_hole()
712 pot > ilog2(2 * I915_GTT_PAGE_SIZE); in pot_hole()
717 for (addr = round_up(hole_start + I915_GTT_PAGE_SIZE, step) - I915_GTT_PAGE_SIZE; in pot_hole()
718 addr <= round_down(hole_end - 2*I915_GTT_PAGE_SIZE, step) - I915_GTT_PAGE_SIZE; in pot_hole()
1355 total + 2 * I915_GTT_PAGE_SIZE <= ggtt->vm.total; in igt_gtt_reserve()
1356 total += 2 * I915_GTT_PAGE_SIZE) { in igt_gtt_reserve()
1396 vma->node.size != 2*I915_GTT_PAGE_SIZE) { in igt_gtt_reserve()
1399 total, 2*I915_GTT_PAGE_SIZE); in igt_gtt_reserve()
1406 for (total = I915_GTT_PAGE_SIZE; in igt_gtt_reserve()
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/drivers/gpu/drm/i915/display/
Dintel_dpt.c46 gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE, in dpt_insert_page()
67 i = vma->node.start / I915_GTT_PAGE_SIZE; in dpt_insert_entries()
95 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; in dpt_bind_vma()
174 size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE); in intel_dpt_create()
176 size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE); in intel_dpt_create()
202 vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE; in intel_dpt_create()
/drivers/gpu/drm/i915/gt/
Dintel_ggtt.c32 *start += I915_GTT_PAGE_SIZE; in i915_ggtt_color_adjust()
42 *end -= I915_GTT_PAGE_SIZE; in i915_ggtt_color_adjust()
216 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE; in gen8_ggtt_insert_page()
241 gte += vma->node.start / I915_GTT_PAGE_SIZE; in gen8_ggtt_insert_entries()
242 end = gte + vma->node.size / I915_GTT_PAGE_SIZE; in gen8_ggtt_insert_entries()
267 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE; in gen6_ggtt_insert_page()
292 gte += vma->node.start / I915_GTT_PAGE_SIZE; in gen6_ggtt_insert_entries()
293 end = gte + vma->node.size / I915_GTT_PAGE_SIZE; in gen6_ggtt_insert_entries()
319 unsigned int first_entry = start / I915_GTT_PAGE_SIZE; in gen8_ggtt_clear_range()
320 unsigned int num_entries = length / I915_GTT_PAGE_SIZE; in gen8_ggtt_clear_range()
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Dselftest_context.c111 vaddr += engine->context_size - I915_GTT_PAGE_SIZE; in __live_context_size()
112 memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE); in __live_context_size()
135 if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE)) { in __live_context_size()
177 engine->context_size += I915_GTT_PAGE_SIZE; in live_context_size()
181 engine->context_size -= I915_GTT_PAGE_SIZE; in live_context_size()
Dgen6_ppgtt.c74 const unsigned int first_entry = start / I915_GTT_PAGE_SIZE; in gen6_ppgtt_clear_range()
78 unsigned int num_entries = length / I915_GTT_PAGE_SIZE; in gen6_ppgtt_clear_range()
113 unsigned int first_entry = vma->node.start / I915_GTT_PAGE_SIZE; in gen6_ppgtt_insert_entries()
124 GEM_BUG_ON(sg_dma_len(iter.sg) < I915_GTT_PAGE_SIZE); in gen6_ppgtt_insert_entries()
127 iter.dma += I915_GTT_PAGE_SIZE; in gen6_ppgtt_insert_entries()
143 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; in gen6_ppgtt_insert_entries()
296 u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE; in pd_vma_bind()
Dgen8_ppgtt.c427 GEM_BUG_ON(sg_dma_len(iter->sg) < I915_GTT_PAGE_SIZE); in gen8_ppgtt_insert_pte()
430 iter->dma += I915_GTT_PAGE_SIZE; in gen8_ppgtt_insert_pte()
496 page_size = I915_GTT_PAGE_SIZE; in gen8_ppgtt_insert_huge()
502 rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE)) in gen8_ppgtt_insert_huge()
530 rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))) in gen8_ppgtt_insert_huge()
589 if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { in gen8_ppgtt_insert()
602 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; in gen8_ppgtt_insert()
Dintel_gtt.h46 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K macro
49 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
51 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
149 __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
Dintel_lrc.c805 memset(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE); in set_redzone()
816 if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE)) in check_redzone()
854 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); in __lrc_alloc_state()
857 context_size += I915_GTT_PAGE_SIZE; /* for redzone */ in __lrc_alloc_state()
1122 GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); in setup_indirect_ctx_bb()
Dintel_migrate.c326 total += I915_GTT_PAGE_SIZE; in emit_pte()
328 it->dma += I915_GTT_PAGE_SIZE; in emit_pte()
Dintel_engine_cs.c177 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE); in intel_engine_context_size()
/drivers/gpu/drm/i915/
Di915_gem_gtt.c103 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); in i915_gem_gtt_reserve()
198 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); in i915_gem_gtt_insert()
202 GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); in i915_gem_gtt_insert()
203 GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); in i915_gem_gtt_insert()
225 BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE); in i915_gem_gtt_insert()
Di915_gem_evict.c275 GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); in i915_gem_evict_for_node()
276 GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); in i915_gem_evict_for_node()
291 start -= I915_GTT_PAGE_SIZE; in i915_gem_evict_for_node()
294 end += I915_GTT_PAGE_SIZE; in i915_gem_evict_for_node()
Di915_vma.c156 GEM_BUG_ON(!IS_ALIGNED(vma->size, I915_GTT_PAGE_SIZE)); in vma_create()
651 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); in i915_vma_insert()
656 GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); in i915_vma_insert()
662 end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE); in i915_vma_insert()
663 GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); in i915_vma_insert()
701 vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { in i915_vma_insert()
Di915_perf.c1874 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE); in alloc_oa_config_buffer()
/drivers/gpu/drm/i915/gvt/
Daperture_gm.c53 start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
54 end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
59 start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
60 end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE); in alloc_gm()
67 size, I915_GTT_PAGE_SIZE, in alloc_gm()
262 vgpu_aperture_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE); in alloc_resource()
273 vgpu_hidden_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE); in alloc_resource()
Dreg.h116 I915_GTT_PAGE_SIZE)
Dscheduler.c184 I915_GTT_PAGE_SIZE - RING_CTX_SIZE); in populate_shadow_context()
238 gpa_size += I915_GTT_PAGE_SIZE; in populate_shadow_context()
248 gpa_size = I915_GTT_PAGE_SIZE; in populate_shadow_context()
1001 gpa_size += I915_GTT_PAGE_SIZE; in update_guest_context()
1011 gpa_size = I915_GTT_PAGE_SIZE; in update_guest_context()
1043 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); in update_guest_context()
Dcmd_parser.c1566 if (guest_gma >= I915_GTT_PAGE_SIZE) { in cmd_address_audit()
1771 offset = gma & (I915_GTT_PAGE_SIZE - 1); in copy_gma_to_hva()
1773 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ? in copy_gma_to_hva()
1774 I915_GTT_PAGE_SIZE - offset : end_gma - gma; in copy_gma_to_hva()
2837 if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE))) in scan_workload()
2882 I915_GTT_PAGE_SIZE))) in scan_wa_ctx()
Dgtt.c909 (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
1456 for (index = 0; index < (I915_GTT_PAGE_SIZE >> in sync_oos_page()
1509 oos_page->mem, I915_GTT_PAGE_SIZE); in attach_oos_page()
2404 int page_entry_num = I915_GTT_PAGE_SIZE >> in alloc_scratch_pages()
Dhandlers.c1742 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { in hws_pga_write()
/drivers/gpu/drm/i915/gem/selftests/
Dhuge_gem_object.c107 GEM_BUG_ON(!IS_ALIGNED(dma_size, I915_GTT_PAGE_SIZE)); in huge_gem_object()
Di915_gem_context.c1520 GEM_BUG_ON(offset < I915_GTT_PAGE_SIZE); in write_to_scratch()
1617 GEM_BUG_ON(offset < I915_GTT_PAGE_SIZE); in read_from_scratch()
1858 I915_GTT_PAGE_SIZE, vm_total, in igt_vm_isolation()
Dhuge_pages.c306 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)); in fake_huge_pages_object()