Home
last modified time | relevance | path

Searched refs:I915_MAX_PIPES (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_bw.h25 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
43 unsigned int data_rate[I915_MAX_PIPES];
44 u8 num_active_planes[I915_MAX_PIPES];
Dintel_cdclk.h43 int min_cdclk[I915_MAX_PIPES];
45 u8 min_voltage_level[I915_MAX_PIPES];
Dintel_frontbuffer.c313 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
Dintel_display.h93 I915_MAX_PIPES = _PIPE_EDP enumerator
349 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
Dintel_dvo.c454 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init()
Dintel_display_types.h1589 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
Dintel_display.c10335 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()
10372 entries, I915_MAX_PIPES, pipe)) in skl_commit_modeset_enables()
10440 entries, I915_MAX_PIPES, pipe)); in skl_commit_modeset_enables()
10565 u64 put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()
/drivers/gpu/drm/i915/
Dintel_pm.h79 struct skl_ddb_entry ddb[I915_MAX_PIPES];
80 unsigned int weight[I915_MAX_PIPES];
81 u8 slices[I915_MAX_PIPES];
Dintel_device_info.h216 int cursor_offsets[I915_MAX_PIPES];
239 u8 num_sprites[I915_MAX_PIPES];
240 u8 num_scalers[I915_MAX_PIPES];
Di915_drv.h916 u32 de_irq_mask[I915_MAX_PIPES];
918 u32 pipestat_irq_mask[I915_MAX_PIPES];
995 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
996 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1085 u32 chv_dpll_md[I915_MAX_PIPES];
1209 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1290 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
Di915_irq.c1400 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument
1466 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument
1483 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument
1507 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument
1534 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument
1634 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()
1721 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()
4038 u32 pipe_stats[I915_MAX_PIPES] = {}; in i8xx_irq_handler()
4141 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()
4287 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
Dintel_pm.c4408 u8 dbuf_mask[I915_MAX_PIPES];
6702 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_dbuf_is_misconfigured()
6723 I915_MAX_PIPES, crtc->pipe)) in skl_dbuf_is_misconfigured()
/drivers/gpu/drm/i915/gvt/
Dfb_decoder.c186 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()
210 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()
341 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()
420 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_sprite_plane()
Dfb_decoder.h163 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
Dgvt.h120 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
Ddisplay.c75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()