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Searched refs:IH_RB_CNTL (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvega10_ih.c106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in vega10_ih_toggle_ring_interrupts()
107 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); in vega10_ih_toggle_ring_interrupts()
110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in vega10_ih_toggle_ring_interrupts()
162 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
164 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega10_ih_rb_cntl()
174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in vega10_ih_rb_cntl()
175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); in vega10_ih_rb_cntl()
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Dtonga_ih.c64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts()
65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in tonga_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in tonga_ih_irq_init()
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); in tonga_ih_irq_init()
219 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_get_wptr()
Dnavi10_ih.c162 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in navi10_ih_toggle_ring_interrupts()
165 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in navi10_ih_toggle_ring_interrupts()
216 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
218 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
220 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
222 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
226 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in navi10_ih_rb_cntl()
228 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in navi10_ih_rb_cntl()
229 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); in navi10_ih_rb_cntl()
230 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in navi10_ih_rb_cntl()
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Dvega20_ih.c109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in vega20_ih_toggle_ring_interrupts()
110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); in vega20_ih_toggle_ring_interrupts()
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in vega20_ih_toggle_ring_interrupts()
166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega20_ih_rb_cntl()
176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, in vega20_ih_rb_cntl()
178 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in vega20_ih_rb_cntl()
179 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); in vega20_ih_rb_cntl()
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Dsi_ih.c38 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
43 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_enable_interrupts()
49 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
54 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_disable_interrupts()
86 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_irq_init()
119 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
121 WREG32(IH_RB_CNTL, tmp); in si_ih_get_wptr()
Diceland_ih.c66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in iceland_ih_irq_init()
215 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_get_wptr()
Dcz_ih.c66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in cz_ih_irq_init()
216 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_get_wptr()
Dsid.h654 #define IH_RB_CNTL 0xF80 macro
/drivers/gpu/drm/radeon/
Dr600.c3593 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts()
3598 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts()
3604 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts()
3609 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts()
3721 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
4055 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr()
4057 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
Dsi.c5922 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts()
5927 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5933 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts()
5938 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
6024 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
6227 tmp = RREG32(IH_RB_CNTL); in si_get_ih_wptr()
6229 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
Dcik.c6815 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts()
6820 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6833 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts()
6838 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
6982 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
7499 tmp = RREG32(IH_RB_CNTL); in cik_get_ih_wptr()
7501 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
Dsid.h651 #define IH_RB_CNTL 0x3e00 macro
Dcikd.h801 #define IH_RB_CNTL 0x3e00 macro
Devergreend.h1220 #define IH_RB_CNTL 0x3e00 macro
Dr600d.h659 #define IH_RB_CNTL 0x3e00 macro
Devergreen.c4695 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
4697 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()