Searched refs:MASTER_COMM_CMD_REG (Results 1 – 5 of 5) sorted by relevance
/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_dmcu.h | 41 SR(MASTER_COMM_CMD_REG), \ 63 SR(MASTER_COMM_CMD_REG), \ 80 SR(MASTER_COMM_CMD_REG), \ 116 DMCU_SF(MASTER_COMM_CMD_REG, \ 144 DMCU_SF(MASTER_COMM_CMD_REG, \ 162 DMCU_SF(MASTER_COMM_CMD_REG, \ 218 uint32_t MASTER_COMM_CMD_REG; member
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D | dce_dmcu.c | 150 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable() 153 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable() 276 REG_UPDATE(MASTER_COMM_CMD_REG, in dce_dmcu_setup_psr() 323 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); in dce_psr_wait_loop() 375 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_enable_fractional_pwm() 430 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_init() 513 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_load_iram() 572 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable() 575 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable() 716 REG_UPDATE(MASTER_COMM_CMD_REG, in dcn10_dmcu_setup_psr() [all …]
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D | dce_abm.h | 34 SR(MASTER_COMM_CMD_REG), \ 120 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 121 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ 122 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) 232 uint32_t MASTER_COMM_CMD_REG; member
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D | dce_abm.c | 73 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_pipe() 118 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); in dmcu_set_backlight_level() 210 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_level()
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D | dce_link_encoder.h | 151 uint32_t MASTER_COMM_CMD_REG; member
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