Searched refs:MASTER_COMM_DATA_REG1 (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_dmcu.h | 38 SR(MASTER_COMM_DATA_REG1), \
60 SR(MASTER_COMM_DATA_REG1), \
77 SR(MASTER_COMM_DATA_REG1), \
215 uint32_t MASTER_COMM_DATA_REG1; member
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| D | dce_dmcu.c | 255 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dce_dmcu_setup_psr()
320 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dce_psr_wait_loop()
372 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); in dcn10_dmcu_enable_fractional_pwm()
422 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); in dcn10_dmcu_init()
694 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_dmcu_setup_psr()
746 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dcn10_psr_wait_loop()
847 REG_WRITE(MASTER_COMM_DATA_REG1, header); in dcn10_send_edid_cea()
963 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_forward_crc_window()
1001 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_stop_crc_win_update()
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| D | dce_abm.c | 70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); in dce_abm_set_pipe()
115 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); in dmcu_set_backlight_level()
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| D | dce_abm.h | 35 SR(MASTER_COMM_DATA_REG1)
233 uint32_t MASTER_COMM_DATA_REG1; member
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| D | dce_link_encoder.h | 148 uint32_t MASTER_COMM_DATA_REG1; member
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