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Searched refs:MAX_DWB_PIPES (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h226 struct dwbc *dwbc[MAX_DWB_PIPES];
227 struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
414 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
/drivers/gpu/drm/amd/display/dc/
Ddc_stream.h100 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
222 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dhw_shared.h40 #define MAX_DWB_PIPES 1 macro
/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c445 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
507 if (dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_remove_writeback()
Ddc.c2516 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES); in copy_stream_update_to_stream()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c227 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_set_writeback()
354 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_disable_writeback()
Ddcn30_resource.c1610 for (j = 0; j < MAX_DWB_PIPES; j++) { in dcn30_set_mcif_arb_params()
1639 if (dwb_pipe >= MAX_DWB_PIPES) in dcn30_set_mcif_arb_params()
1642 if (dwb_pipe >= MAX_DWB_PIPES) in dcn30_set_mcif_arb_params()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c1938 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_enable_writeback()
1963 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_disable_writeback()
Ddcn20_resource.c2415 for (j = 0; j < MAX_DWB_PIPES; j++) { in dcn20_set_mcif_arb_params()
2443 if (dwb_pipe >= MAX_DWB_PIPES) in dcn20_set_mcif_arb_params()
2446 if (dwb_pipe >= MAX_DWB_PIPES) in dcn20_set_mcif_arb_params()