Searched refs:MPLL_DQ_FUNC_CNTL (Results 1 – 16 of 16) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| D | rv740d.h | 63 #define MPLL_DQ_FUNC_CNTL 0x62c macro
|
| D | rv740_dpm.c | 307 RREG32(MPLL_DQ_FUNC_CNTL); in rv740_read_clock_registers()
|
| D | rv770d.h | 136 #define MPLL_DQ_FUNC_CNTL 0x62c macro
|
| D | nid.h | 578 #define MPLL_DQ_FUNC_CNTL 0x62c macro
|
| D | sid.h | 626 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
|
| D | cikd.h | 749 #define MPLL_DQ_FUNC_CNTL 0x2bc4 macro
|
| D | evergreend.h | 116 #define MPLL_DQ_FUNC_CNTL 0x62c macro
|
| D | rv770_dpm.c | 1537 RREG32(MPLL_DQ_FUNC_CNTL); in rv770_read_clock_registers()
|
| D | ni_dpm.c | 1191 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ni_read_clock_registers()
|
| D | ci_dpm.c | 1853 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
|
| D | si_dpm.c | 3561 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
|
| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | iceland_smumgr.c | 1090 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in iceland_calculate_mclk_params()
1092 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
|
| D | ci_smumgr.c | 1063 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel); in ci_calculate_mclk_params()
1065 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
|
| D | tonga_smumgr.c | 840 MPLL_DQ_FUNC_CNTL, YCLK_SEL, in tonga_calculate_mclk_params()
843 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, in tonga_calculate_mclk_params()
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | sid.h | 627 #define MPLL_DQ_FUNC_CNTL 0xAF1 macro
|
| /drivers/gpu/drm/amd/pm/powerplay/ |
| D | si_dpm.c | 4020 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
|