1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell 10G 88x3310 PHY driver
4 *
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
7 *
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
11 *
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 *
16 * With XAUI, observation shows:
17 *
18 * XAUI PHYXS -- <appropriate PCS as above>
19 *
20 * and no switching of the host interface mode occurs.
21 *
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
24 */
25 #include <linux/ctype.h>
26 #include <linux/delay.h>
27 #include <linux/hwmon.h>
28 #include <linux/marvell_phy.h>
29 #include <linux/phy.h>
30 #include <linux/sfp.h>
31 #include <linux/netdevice.h>
32
33 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
34 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
35
36 enum {
37 MV_PMA_FW_VER0 = 0xc011,
38 MV_PMA_FW_VER1 = 0xc012,
39 MV_PMA_21X0_PORT_CTRL = 0xc04a,
40 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
41 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
42 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
43 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
44 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
45 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
46 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
47 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
48 MV_PMA_BOOT = 0xc050,
49 MV_PMA_BOOT_FATAL = BIT(0),
50
51 MV_PCS_BASE_T = 0x0000,
52 MV_PCS_BASE_R = 0x1000,
53 MV_PCS_1000BASEX = 0x2000,
54
55 MV_PCS_CSCR1 = 0x8000,
56 MV_PCS_CSCR1_ED_MASK = 0x0300,
57 MV_PCS_CSCR1_ED_OFF = 0x0000,
58 MV_PCS_CSCR1_ED_RX = 0x0200,
59 MV_PCS_CSCR1_ED_NLP = 0x0300,
60 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
61 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
62 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
63 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
64
65 MV_PCS_CSSR1 = 0x8008,
66 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
67 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
68 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
69 MV_PCS_CSSR1_SPD1_100 = 0x4000,
70 MV_PCS_CSSR1_SPD1_10 = 0x0000,
71 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
72 MV_PCS_CSSR1_RESOLVED = BIT(11),
73 MV_PCS_CSSR1_MDIX = BIT(6),
74 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
75 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
76 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
77 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
78
79 /* Temperature read register (88E2110 only) */
80 MV_PCS_TEMP = 0x8042,
81
82 /* Number of ports on the device */
83 MV_PCS_PORT_INFO = 0xd00d,
84 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
85 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
86
87 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
88 * registers appear to set themselves to the 0x800X when AN is
89 * restarted, but status registers appear readable from either.
90 */
91 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
92 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
93
94 /* Vendor2 MMD registers */
95 MV_V2_PORT_CTRL = 0xf001,
96 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
97 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
98 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
99 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
100 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
101 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
102 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
103 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
104 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
105 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
106 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
107 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
108 MV_V2_PORT_INTR_STS = 0xf040,
109 MV_V2_PORT_INTR_MASK = 0xf043,
110 MV_V2_PORT_INTR_STS_WOL_EN = BIT(8),
111 MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
112 MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
113 MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
114 /* Wake on LAN registers */
115 MV_V2_WOL_CTRL = 0xf06e,
116 MV_V2_WOL_CTRL_CLEAR_STS = BIT(15),
117 MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0),
118 /* Temperature control/read registers (88X3310 only) */
119 MV_V2_TEMP_CTRL = 0xf08a,
120 MV_V2_TEMP_CTRL_MASK = 0xc000,
121 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
122 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
123 MV_V2_TEMP = 0xf08c,
124 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
125 };
126
127 struct mv3310_chip {
128 void (*init_supported_interfaces)(unsigned long *mask);
129 int (*get_mactype)(struct phy_device *phydev);
130 int (*init_interface)(struct phy_device *phydev, int mactype);
131
132 #ifdef CONFIG_HWMON
133 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
134 #endif
135 };
136
137 struct mv3310_priv {
138 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
139
140 u32 firmware_ver;
141 bool rate_match;
142 phy_interface_t const_interface;
143
144 struct device *hwmon_dev;
145 char *hwmon_name;
146 };
147
to_mv3310_chip(struct phy_device * phydev)148 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
149 {
150 return phydev->drv->driver_data;
151 }
152
153 #ifdef CONFIG_HWMON
mv3310_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)154 static umode_t mv3310_hwmon_is_visible(const void *data,
155 enum hwmon_sensor_types type,
156 u32 attr, int channel)
157 {
158 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
159 return 0444;
160 if (type == hwmon_temp && attr == hwmon_temp_input)
161 return 0444;
162 return 0;
163 }
164
mv3310_hwmon_read_temp_reg(struct phy_device * phydev)165 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
166 {
167 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
168 }
169
mv2110_hwmon_read_temp_reg(struct phy_device * phydev)170 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
171 {
172 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
173 }
174
mv3310_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)175 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
176 u32 attr, int channel, long *value)
177 {
178 struct phy_device *phydev = dev_get_drvdata(dev);
179 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
180 int temp;
181
182 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
183 *value = MSEC_PER_SEC;
184 return 0;
185 }
186
187 if (type == hwmon_temp && attr == hwmon_temp_input) {
188 temp = chip->hwmon_read_temp_reg(phydev);
189 if (temp < 0)
190 return temp;
191
192 *value = ((temp & 0xff) - 75) * 1000;
193
194 return 0;
195 }
196
197 return -EOPNOTSUPP;
198 }
199
200 static const struct hwmon_ops mv3310_hwmon_ops = {
201 .is_visible = mv3310_hwmon_is_visible,
202 .read = mv3310_hwmon_read,
203 };
204
205 static u32 mv3310_hwmon_chip_config[] = {
206 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
207 0,
208 };
209
210 static const struct hwmon_channel_info mv3310_hwmon_chip = {
211 .type = hwmon_chip,
212 .config = mv3310_hwmon_chip_config,
213 };
214
215 static u32 mv3310_hwmon_temp_config[] = {
216 HWMON_T_INPUT,
217 0,
218 };
219
220 static const struct hwmon_channel_info mv3310_hwmon_temp = {
221 .type = hwmon_temp,
222 .config = mv3310_hwmon_temp_config,
223 };
224
225 static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
226 &mv3310_hwmon_chip,
227 &mv3310_hwmon_temp,
228 NULL,
229 };
230
231 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
232 .ops = &mv3310_hwmon_ops,
233 .info = mv3310_hwmon_info,
234 };
235
mv3310_hwmon_config(struct phy_device * phydev,bool enable)236 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
237 {
238 u16 val;
239 int ret;
240
241 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
242 return 0;
243
244 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
245 MV_V2_TEMP_UNKNOWN);
246 if (ret < 0)
247 return ret;
248
249 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
250
251 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
252 MV_V2_TEMP_CTRL_MASK, val);
253 }
254
mv3310_hwmon_probe(struct phy_device * phydev)255 static int mv3310_hwmon_probe(struct phy_device *phydev)
256 {
257 struct device *dev = &phydev->mdio.dev;
258 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
259 int i, j, ret;
260
261 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
262 if (!priv->hwmon_name)
263 return -ENODEV;
264
265 for (i = j = 0; priv->hwmon_name[i]; i++) {
266 if (isalnum(priv->hwmon_name[i])) {
267 if (i != j)
268 priv->hwmon_name[j] = priv->hwmon_name[i];
269 j++;
270 }
271 }
272 priv->hwmon_name[j] = '\0';
273
274 ret = mv3310_hwmon_config(phydev, true);
275 if (ret)
276 return ret;
277
278 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
279 priv->hwmon_name, phydev,
280 &mv3310_hwmon_chip_info, NULL);
281
282 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
283 }
284 #else
mv3310_hwmon_config(struct phy_device * phydev,bool enable)285 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
286 {
287 return 0;
288 }
289
mv3310_hwmon_probe(struct phy_device * phydev)290 static int mv3310_hwmon_probe(struct phy_device *phydev)
291 {
292 return 0;
293 }
294 #endif
295
mv3310_power_down(struct phy_device * phydev)296 static int mv3310_power_down(struct phy_device *phydev)
297 {
298 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
299 MV_V2_PORT_CTRL_PWRDOWN);
300 }
301
mv3310_power_up(struct phy_device * phydev)302 static int mv3310_power_up(struct phy_device *phydev)
303 {
304 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
305 int ret;
306
307 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
308 MV_V2_PORT_CTRL_PWRDOWN);
309
310 /* Sometimes, the power down bit doesn't clear immediately, and
311 * a read of this register causes the bit not to clear. Delay
312 * 100us to allow the PHY to come out of power down mode before
313 * the next access.
314 */
315 udelay(100);
316
317 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
318 priv->firmware_ver < 0x00030000)
319 return ret;
320
321 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
322 MV_V2_33X0_PORT_CTRL_SWRST);
323 }
324
mv3310_reset(struct phy_device * phydev,u32 unit)325 static int mv3310_reset(struct phy_device *phydev, u32 unit)
326 {
327 int val, err;
328
329 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
330 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
331 if (err < 0)
332 return err;
333
334 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
335 unit + MDIO_CTRL1, val,
336 !(val & MDIO_CTRL1_RESET),
337 5000, 100000, true);
338 }
339
mv3310_get_edpd(struct phy_device * phydev,u16 * edpd)340 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
341 {
342 int val;
343
344 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
345 if (val < 0)
346 return val;
347
348 switch (val & MV_PCS_CSCR1_ED_MASK) {
349 case MV_PCS_CSCR1_ED_NLP:
350 *edpd = 1000;
351 break;
352 case MV_PCS_CSCR1_ED_RX:
353 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
354 break;
355 default:
356 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
357 break;
358 }
359 return 0;
360 }
361
mv3310_set_edpd(struct phy_device * phydev,u16 edpd)362 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
363 {
364 u16 val;
365 int err;
366
367 switch (edpd) {
368 case 1000:
369 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
370 val = MV_PCS_CSCR1_ED_NLP;
371 break;
372
373 case ETHTOOL_PHY_EDPD_NO_TX:
374 val = MV_PCS_CSCR1_ED_RX;
375 break;
376
377 case ETHTOOL_PHY_EDPD_DISABLE:
378 val = MV_PCS_CSCR1_ED_OFF;
379 break;
380
381 default:
382 return -EINVAL;
383 }
384
385 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
386 MV_PCS_CSCR1_ED_MASK, val);
387 if (err > 0)
388 err = mv3310_reset(phydev, MV_PCS_BASE_T);
389
390 return err;
391 }
392
mv3310_sfp_insert(void * upstream,const struct sfp_eeprom_id * id)393 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
394 {
395 struct phy_device *phydev = upstream;
396 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
397 phy_interface_t iface;
398
399 sfp_parse_support(phydev->sfp_bus, id, support);
400 iface = sfp_select_interface(phydev->sfp_bus, support);
401
402 if (iface != PHY_INTERFACE_MODE_10GBASER) {
403 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
404 return -EINVAL;
405 }
406 return 0;
407 }
408
409 static const struct sfp_upstream_ops mv3310_sfp_ops = {
410 .attach = phy_sfp_attach,
411 .detach = phy_sfp_detach,
412 .module_insert = mv3310_sfp_insert,
413 };
414
mv3310_probe(struct phy_device * phydev)415 static int mv3310_probe(struct phy_device *phydev)
416 {
417 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
418 struct mv3310_priv *priv;
419 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
420 int ret;
421
422 if (!phydev->is_c45 ||
423 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
424 return -ENODEV;
425
426 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
427 if (ret < 0)
428 return ret;
429
430 if (ret & MV_PMA_BOOT_FATAL) {
431 dev_warn(&phydev->mdio.dev,
432 "PHY failed to boot firmware, status=%04x\n", ret);
433 return -ENODEV;
434 }
435
436 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
437 if (!priv)
438 return -ENOMEM;
439
440 dev_set_drvdata(&phydev->mdio.dev, priv);
441
442 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
443 if (ret < 0)
444 return ret;
445
446 priv->firmware_ver = ret << 16;
447
448 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
449 if (ret < 0)
450 return ret;
451
452 priv->firmware_ver |= ret;
453
454 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
455 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
456 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
457
458 /* Powering down the port when not in use saves about 600mW */
459 ret = mv3310_power_down(phydev);
460 if (ret)
461 return ret;
462
463 ret = mv3310_hwmon_probe(phydev);
464 if (ret)
465 return ret;
466
467 chip->init_supported_interfaces(priv->supported_interfaces);
468
469 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
470 }
471
mv3310_remove(struct phy_device * phydev)472 static void mv3310_remove(struct phy_device *phydev)
473 {
474 mv3310_hwmon_config(phydev, false);
475 }
476
mv3310_suspend(struct phy_device * phydev)477 static int mv3310_suspend(struct phy_device *phydev)
478 {
479 return mv3310_power_down(phydev);
480 }
481
mv3310_resume(struct phy_device * phydev)482 static int mv3310_resume(struct phy_device *phydev)
483 {
484 int ret;
485
486 ret = mv3310_power_up(phydev);
487 if (ret)
488 return ret;
489
490 return mv3310_hwmon_config(phydev, true);
491 }
492
493 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
494 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
495 * support 2.5GBASET and 5GBASET. For these models, we can still read their
496 * 2.5G/5G extended abilities register (1.21). We detect these models based on
497 * the PMA device identifier, with a mask matching models known to have this
498 * issue
499 */
mv3310_has_pma_ngbaset_quirk(struct phy_device * phydev)500 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
501 {
502 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
503 return false;
504
505 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
506 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
507 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
508 }
509
mv2110_get_mactype(struct phy_device * phydev)510 static int mv2110_get_mactype(struct phy_device *phydev)
511 {
512 int mactype;
513
514 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
515 if (mactype < 0)
516 return mactype;
517
518 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
519 }
520
mv3310_get_mactype(struct phy_device * phydev)521 static int mv3310_get_mactype(struct phy_device *phydev)
522 {
523 int mactype;
524
525 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
526 if (mactype < 0)
527 return mactype;
528
529 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
530 }
531
mv2110_init_interface(struct phy_device * phydev,int mactype)532 static int mv2110_init_interface(struct phy_device *phydev, int mactype)
533 {
534 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
535
536 priv->rate_match = false;
537
538 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
539 priv->rate_match = true;
540
541 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
542 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
543 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
544 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
545 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
546 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
547 priv->const_interface = PHY_INTERFACE_MODE_NA;
548 else
549 return -EINVAL;
550
551 return 0;
552 }
553
mv3310_init_interface(struct phy_device * phydev,int mactype)554 static int mv3310_init_interface(struct phy_device *phydev, int mactype)
555 {
556 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
557
558 priv->rate_match = false;
559
560 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
561 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
562 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
563 priv->rate_match = true;
564
565 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
566 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
567 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
568 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
569 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
570 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
571 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
572 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
573 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
574 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
575 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
576 priv->const_interface = PHY_INTERFACE_MODE_XAUI;
577 else
578 return -EINVAL;
579
580 return 0;
581 }
582
mv3340_init_interface(struct phy_device * phydev,int mactype)583 static int mv3340_init_interface(struct phy_device *phydev, int mactype)
584 {
585 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
586 int err = 0;
587
588 priv->rate_match = false;
589
590 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
591 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
592 else
593 err = mv3310_init_interface(phydev, mactype);
594
595 return err;
596 }
597
mv3310_config_init(struct phy_device * phydev)598 static int mv3310_config_init(struct phy_device *phydev)
599 {
600 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
601 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
602 int err, mactype;
603
604 /* Check that the PHY interface type is compatible */
605 if (!test_bit(phydev->interface, priv->supported_interfaces))
606 return -ENODEV;
607
608 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
609
610 /* Power up so reset works */
611 err = mv3310_power_up(phydev);
612 if (err)
613 return err;
614
615 mactype = chip->get_mactype(phydev);
616 if (mactype < 0)
617 return mactype;
618
619 err = chip->init_interface(phydev, mactype);
620 if (err) {
621 phydev_err(phydev, "MACTYPE configuration invalid\n");
622 return err;
623 }
624
625 /* Enable EDPD mode - saving 600mW */
626 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
627 }
628
mv3310_get_features(struct phy_device * phydev)629 static int mv3310_get_features(struct phy_device *phydev)
630 {
631 int ret, val;
632
633 ret = genphy_c45_pma_read_abilities(phydev);
634 if (ret)
635 return ret;
636
637 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
638 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
639 MDIO_PMA_NG_EXTABLE);
640 if (val < 0)
641 return val;
642
643 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
644 phydev->supported,
645 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
646
647 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
648 phydev->supported,
649 val & MDIO_PMA_NG_EXTABLE_5GBT);
650 }
651
652 return 0;
653 }
654
mv3310_config_mdix(struct phy_device * phydev)655 static int mv3310_config_mdix(struct phy_device *phydev)
656 {
657 u16 val;
658 int err;
659
660 switch (phydev->mdix_ctrl) {
661 case ETH_TP_MDI_AUTO:
662 val = MV_PCS_CSCR1_MDIX_AUTO;
663 break;
664 case ETH_TP_MDI_X:
665 val = MV_PCS_CSCR1_MDIX_MDIX;
666 break;
667 case ETH_TP_MDI:
668 val = MV_PCS_CSCR1_MDIX_MDI;
669 break;
670 default:
671 return -EINVAL;
672 }
673
674 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
675 MV_PCS_CSCR1_MDIX_MASK, val);
676 if (err > 0)
677 err = mv3310_reset(phydev, MV_PCS_BASE_T);
678
679 return err;
680 }
681
mv3310_config_aneg(struct phy_device * phydev)682 static int mv3310_config_aneg(struct phy_device *phydev)
683 {
684 bool changed = false;
685 u16 reg;
686 int ret;
687
688 ret = mv3310_config_mdix(phydev);
689 if (ret < 0)
690 return ret;
691
692 if (phydev->autoneg == AUTONEG_DISABLE)
693 return genphy_c45_pma_setup_forced(phydev);
694
695 ret = genphy_c45_an_config_aneg(phydev);
696 if (ret < 0)
697 return ret;
698 if (ret > 0)
699 changed = true;
700
701 /* Clause 45 has no standardized support for 1000BaseT, therefore
702 * use vendor registers for this mode.
703 */
704 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
705 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
706 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
707 if (ret < 0)
708 return ret;
709 if (ret > 0)
710 changed = true;
711
712 return genphy_c45_check_and_restart_aneg(phydev, changed);
713 }
714
mv3310_aneg_done(struct phy_device * phydev)715 static int mv3310_aneg_done(struct phy_device *phydev)
716 {
717 int val;
718
719 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
720 if (val < 0)
721 return val;
722
723 if (val & MDIO_STAT1_LSTATUS)
724 return 1;
725
726 return genphy_c45_aneg_done(phydev);
727 }
728
mv3310_update_interface(struct phy_device * phydev)729 static void mv3310_update_interface(struct phy_device *phydev)
730 {
731 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
732
733 if (!phydev->link)
734 return;
735
736 /* In all of the "* with Rate Matching" modes the PHY interface is fixed
737 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
738 * internal 16KB buffer.
739 *
740 * In USXGMII mode the PHY interface mode is also fixed.
741 */
742 if (priv->rate_match ||
743 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
744 phydev->interface = priv->const_interface;
745 return;
746 }
747
748 /* The PHY automatically switches its serdes interface (and active PHYXS
749 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
750 * xaui / rxaui modes according to the speed.
751 * Florian suggests setting phydev->interface to communicate this to the
752 * MAC. Only do this if we are already in one of the above modes.
753 */
754 switch (phydev->speed) {
755 case SPEED_10000:
756 phydev->interface = priv->const_interface;
757 break;
758 case SPEED_5000:
759 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
760 break;
761 case SPEED_2500:
762 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
763 break;
764 case SPEED_1000:
765 case SPEED_100:
766 case SPEED_10:
767 phydev->interface = PHY_INTERFACE_MODE_SGMII;
768 break;
769 default:
770 break;
771 }
772 }
773
774 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
mv3310_read_status_10gbaser(struct phy_device * phydev)775 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
776 {
777 phydev->link = 1;
778 phydev->speed = SPEED_10000;
779 phydev->duplex = DUPLEX_FULL;
780 phydev->port = PORT_FIBRE;
781
782 return 0;
783 }
784
mv3310_read_status_copper(struct phy_device * phydev)785 static int mv3310_read_status_copper(struct phy_device *phydev)
786 {
787 int cssr1, speed, val;
788
789 val = genphy_c45_read_link(phydev);
790 if (val < 0)
791 return val;
792
793 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
794 if (val < 0)
795 return val;
796
797 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
798 if (cssr1 < 0)
799 return cssr1;
800
801 /* If the link settings are not resolved, mark the link down */
802 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
803 phydev->link = 0;
804 return 0;
805 }
806
807 /* Read the copper link settings */
808 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
809 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
810 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
811
812 switch (speed) {
813 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
814 phydev->speed = SPEED_10000;
815 break;
816
817 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
818 phydev->speed = SPEED_5000;
819 break;
820
821 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
822 phydev->speed = SPEED_2500;
823 break;
824
825 case MV_PCS_CSSR1_SPD1_1000:
826 phydev->speed = SPEED_1000;
827 break;
828
829 case MV_PCS_CSSR1_SPD1_100:
830 phydev->speed = SPEED_100;
831 break;
832
833 case MV_PCS_CSSR1_SPD1_10:
834 phydev->speed = SPEED_10;
835 break;
836 }
837
838 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
839 DUPLEX_FULL : DUPLEX_HALF;
840 phydev->port = PORT_TP;
841 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
842 ETH_TP_MDI_X : ETH_TP_MDI;
843
844 if (val & MDIO_AN_STAT1_COMPLETE) {
845 val = genphy_c45_read_lpa(phydev);
846 if (val < 0)
847 return val;
848
849 /* Read the link partner's 1G advertisement */
850 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
851 if (val < 0)
852 return val;
853
854 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
855
856 /* Update the pause status */
857 phy_resolve_aneg_pause(phydev);
858 }
859
860 return 0;
861 }
862
mv3310_read_status(struct phy_device * phydev)863 static int mv3310_read_status(struct phy_device *phydev)
864 {
865 int err, val;
866
867 phydev->speed = SPEED_UNKNOWN;
868 phydev->duplex = DUPLEX_UNKNOWN;
869 linkmode_zero(phydev->lp_advertising);
870 phydev->link = 0;
871 phydev->pause = 0;
872 phydev->asym_pause = 0;
873 phydev->mdix = ETH_TP_MDI_INVALID;
874
875 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
876 if (val < 0)
877 return val;
878
879 if (val & MDIO_STAT1_LSTATUS)
880 err = mv3310_read_status_10gbaser(phydev);
881 else
882 err = mv3310_read_status_copper(phydev);
883 if (err < 0)
884 return err;
885
886 if (phydev->link)
887 mv3310_update_interface(phydev);
888
889 return 0;
890 }
891
mv3310_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)892 static int mv3310_get_tunable(struct phy_device *phydev,
893 struct ethtool_tunable *tuna, void *data)
894 {
895 switch (tuna->id) {
896 case ETHTOOL_PHY_EDPD:
897 return mv3310_get_edpd(phydev, data);
898 default:
899 return -EOPNOTSUPP;
900 }
901 }
902
mv3310_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)903 static int mv3310_set_tunable(struct phy_device *phydev,
904 struct ethtool_tunable *tuna, const void *data)
905 {
906 switch (tuna->id) {
907 case ETHTOOL_PHY_EDPD:
908 return mv3310_set_edpd(phydev, *(u16 *)data);
909 default:
910 return -EOPNOTSUPP;
911 }
912 }
913
mv3310_init_supported_interfaces(unsigned long * mask)914 static void mv3310_init_supported_interfaces(unsigned long *mask)
915 {
916 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
917 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
918 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
919 __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
920 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
921 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
922 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
923 }
924
mv3340_init_supported_interfaces(unsigned long * mask)925 static void mv3340_init_supported_interfaces(unsigned long *mask)
926 {
927 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
928 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
929 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
930 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
931 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
932 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
933 }
934
mv2110_init_supported_interfaces(unsigned long * mask)935 static void mv2110_init_supported_interfaces(unsigned long *mask)
936 {
937 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
938 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
939 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
940 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
941 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
942 }
943
mv2111_init_supported_interfaces(unsigned long * mask)944 static void mv2111_init_supported_interfaces(unsigned long *mask)
945 {
946 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
947 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
948 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
949 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
950 }
951
952 static const struct mv3310_chip mv3310_type = {
953 .init_supported_interfaces = mv3310_init_supported_interfaces,
954 .get_mactype = mv3310_get_mactype,
955 .init_interface = mv3310_init_interface,
956
957 #ifdef CONFIG_HWMON
958 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
959 #endif
960 };
961
962 static const struct mv3310_chip mv3340_type = {
963 .init_supported_interfaces = mv3340_init_supported_interfaces,
964 .get_mactype = mv3310_get_mactype,
965 .init_interface = mv3340_init_interface,
966
967 #ifdef CONFIG_HWMON
968 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
969 #endif
970 };
971
972 static const struct mv3310_chip mv2110_type = {
973 .init_supported_interfaces = mv2110_init_supported_interfaces,
974 .get_mactype = mv2110_get_mactype,
975 .init_interface = mv2110_init_interface,
976
977 #ifdef CONFIG_HWMON
978 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
979 #endif
980 };
981
982 static const struct mv3310_chip mv2111_type = {
983 .init_supported_interfaces = mv2111_init_supported_interfaces,
984 .get_mactype = mv2110_get_mactype,
985 .init_interface = mv2110_init_interface,
986
987 #ifdef CONFIG_HWMON
988 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
989 #endif
990 };
991
mv3310_get_number_of_ports(struct phy_device * phydev)992 static int mv3310_get_number_of_ports(struct phy_device *phydev)
993 {
994 int ret;
995
996 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
997 if (ret < 0)
998 return ret;
999
1000 ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
1001 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
1002
1003 return ret + 1;
1004 }
1005
mv3310_match_phy_device(struct phy_device * phydev)1006 static int mv3310_match_phy_device(struct phy_device *phydev)
1007 {
1008 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1009 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1010 return 0;
1011
1012 return mv3310_get_number_of_ports(phydev) == 1;
1013 }
1014
mv3340_match_phy_device(struct phy_device * phydev)1015 static int mv3340_match_phy_device(struct phy_device *phydev)
1016 {
1017 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1018 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1019 return 0;
1020
1021 return mv3310_get_number_of_ports(phydev) == 4;
1022 }
1023
mv211x_match_phy_device(struct phy_device * phydev,bool has_5g)1024 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1025 {
1026 int val;
1027
1028 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1029 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
1030 return 0;
1031
1032 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1033 if (val < 0)
1034 return val;
1035
1036 return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
1037 }
1038
mv2110_match_phy_device(struct phy_device * phydev)1039 static int mv2110_match_phy_device(struct phy_device *phydev)
1040 {
1041 return mv211x_match_phy_device(phydev, true);
1042 }
1043
mv2111_match_phy_device(struct phy_device * phydev)1044 static int mv2111_match_phy_device(struct phy_device *phydev)
1045 {
1046 return mv211x_match_phy_device(phydev, false);
1047 }
1048
mv3110_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)1049 static void mv3110_get_wol(struct phy_device *phydev,
1050 struct ethtool_wolinfo *wol)
1051 {
1052 int ret;
1053
1054 wol->supported = WAKE_MAGIC;
1055 wol->wolopts = 0;
1056
1057 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL);
1058 if (ret < 0)
1059 return;
1060
1061 if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN)
1062 wol->wolopts |= WAKE_MAGIC;
1063 }
1064
mv3110_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)1065 static int mv3110_set_wol(struct phy_device *phydev,
1066 struct ethtool_wolinfo *wol)
1067 {
1068 int ret;
1069
1070 if (wol->wolopts & WAKE_MAGIC) {
1071 /* Enable the WOL interrupt */
1072 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1073 MV_V2_PORT_INTR_MASK,
1074 MV_V2_PORT_INTR_STS_WOL_EN);
1075 if (ret < 0)
1076 return ret;
1077
1078 /* Store the device address for the magic packet */
1079 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1080 MV_V2_MAGIC_PKT_WORD2,
1081 ((phydev->attached_dev->dev_addr[5] << 8) |
1082 phydev->attached_dev->dev_addr[4]));
1083 if (ret < 0)
1084 return ret;
1085
1086 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1087 MV_V2_MAGIC_PKT_WORD1,
1088 ((phydev->attached_dev->dev_addr[3] << 8) |
1089 phydev->attached_dev->dev_addr[2]));
1090 if (ret < 0)
1091 return ret;
1092
1093 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1094 MV_V2_MAGIC_PKT_WORD0,
1095 ((phydev->attached_dev->dev_addr[1] << 8) |
1096 phydev->attached_dev->dev_addr[0]));
1097 if (ret < 0)
1098 return ret;
1099
1100 /* Clear WOL status and enable magic packet matching */
1101 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1102 MV_V2_WOL_CTRL,
1103 MV_V2_WOL_CTRL_MAGIC_PKT_EN |
1104 MV_V2_WOL_CTRL_CLEAR_STS);
1105 if (ret < 0)
1106 return ret;
1107 } else {
1108 /* Disable magic packet matching & reset WOL status bit */
1109 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1110 MV_V2_WOL_CTRL,
1111 MV_V2_WOL_CTRL_MAGIC_PKT_EN,
1112 MV_V2_WOL_CTRL_CLEAR_STS);
1113 if (ret < 0)
1114 return ret;
1115 }
1116
1117 /* Reset the clear WOL status bit as it does not self-clear */
1118 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1119 MV_V2_WOL_CTRL,
1120 MV_V2_WOL_CTRL_CLEAR_STS);
1121 }
1122
1123 static struct phy_driver mv3310_drivers[] = {
1124 {
1125 .phy_id = MARVELL_PHY_ID_88X3310,
1126 .phy_id_mask = MARVELL_PHY_ID_MASK,
1127 .match_phy_device = mv3310_match_phy_device,
1128 .name = "mv88x3310",
1129 .driver_data = &mv3310_type,
1130 .get_features = mv3310_get_features,
1131 .config_init = mv3310_config_init,
1132 .probe = mv3310_probe,
1133 .suspend = mv3310_suspend,
1134 .resume = mv3310_resume,
1135 .config_aneg = mv3310_config_aneg,
1136 .aneg_done = mv3310_aneg_done,
1137 .read_status = mv3310_read_status,
1138 .get_tunable = mv3310_get_tunable,
1139 .set_tunable = mv3310_set_tunable,
1140 .remove = mv3310_remove,
1141 .set_loopback = genphy_c45_loopback,
1142 .get_wol = mv3110_get_wol,
1143 .set_wol = mv3110_set_wol,
1144 },
1145 {
1146 .phy_id = MARVELL_PHY_ID_88X3310,
1147 .phy_id_mask = MARVELL_PHY_ID_MASK,
1148 .match_phy_device = mv3340_match_phy_device,
1149 .name = "mv88x3340",
1150 .driver_data = &mv3340_type,
1151 .get_features = mv3310_get_features,
1152 .config_init = mv3310_config_init,
1153 .probe = mv3310_probe,
1154 .suspend = mv3310_suspend,
1155 .resume = mv3310_resume,
1156 .config_aneg = mv3310_config_aneg,
1157 .aneg_done = mv3310_aneg_done,
1158 .read_status = mv3310_read_status,
1159 .get_tunable = mv3310_get_tunable,
1160 .set_tunable = mv3310_set_tunable,
1161 .remove = mv3310_remove,
1162 .set_loopback = genphy_c45_loopback,
1163 },
1164 {
1165 .phy_id = MARVELL_PHY_ID_88E2110,
1166 .phy_id_mask = MARVELL_PHY_ID_MASK,
1167 .match_phy_device = mv2110_match_phy_device,
1168 .name = "mv88e2110",
1169 .driver_data = &mv2110_type,
1170 .probe = mv3310_probe,
1171 .suspend = mv3310_suspend,
1172 .resume = mv3310_resume,
1173 .config_init = mv3310_config_init,
1174 .config_aneg = mv3310_config_aneg,
1175 .aneg_done = mv3310_aneg_done,
1176 .read_status = mv3310_read_status,
1177 .get_tunable = mv3310_get_tunable,
1178 .set_tunable = mv3310_set_tunable,
1179 .remove = mv3310_remove,
1180 .set_loopback = genphy_c45_loopback,
1181 .get_wol = mv3110_get_wol,
1182 .set_wol = mv3110_set_wol,
1183 },
1184 {
1185 .phy_id = MARVELL_PHY_ID_88E2110,
1186 .phy_id_mask = MARVELL_PHY_ID_MASK,
1187 .match_phy_device = mv2111_match_phy_device,
1188 .name = "mv88e2111",
1189 .driver_data = &mv2111_type,
1190 .probe = mv3310_probe,
1191 .suspend = mv3310_suspend,
1192 .resume = mv3310_resume,
1193 .config_init = mv3310_config_init,
1194 .config_aneg = mv3310_config_aneg,
1195 .aneg_done = mv3310_aneg_done,
1196 .read_status = mv3310_read_status,
1197 .get_tunable = mv3310_get_tunable,
1198 .set_tunable = mv3310_set_tunable,
1199 .remove = mv3310_remove,
1200 .set_loopback = genphy_c45_loopback,
1201 },
1202 };
1203
1204 module_phy_driver(mv3310_drivers);
1205
1206 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1207 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
1208 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
1209 { },
1210 };
1211 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1212 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
1213 MODULE_LICENSE("GPL");
1214