| /drivers/cpufreq/ |
| D | speedstep-centrino.c | 85 #define OP(mhz, mv) \ macro
101 OP(600, 844),
102 OP(800, 988),
103 OP(900, 1004),
110 OP(600, 844),
111 OP(800, 972),
112 OP(900, 988),
113 OP(1000, 1004),
120 OP( 600, 956),
121 OP( 800, 1020),
[all …]
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| D | pxa3xx-cpufreq.c | 51 #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \ macro
67 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
68 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
69 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
70 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
75 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
76 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
77 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
78 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
79 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
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| /drivers/infiniband/hw/qib/ |
| D | qib_uc.c | 38 #define OP(x) IB_OPCODE_UC_##x macro
109 qp->s_state = OP(SEND_FIRST); in qib_make_uc_req()
114 qp->s_state = OP(SEND_ONLY); in qib_make_uc_req()
117 OP(SEND_ONLY_WITH_IMMEDIATE); in qib_make_uc_req()
138 qp->s_state = OP(RDMA_WRITE_FIRST); in qib_make_uc_req()
143 qp->s_state = OP(RDMA_WRITE_ONLY); in qib_make_uc_req()
146 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE); in qib_make_uc_req()
163 case OP(SEND_FIRST): in qib_make_uc_req()
164 qp->s_state = OP(SEND_MIDDLE); in qib_make_uc_req()
166 case OP(SEND_MIDDLE): in qib_make_uc_req()
[all …]
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| D | qib_rc.c | 39 #define OP(x) IB_OPCODE_RC_##x macro
79 case OP(RDMA_READ_RESPONSE_LAST): in qib_make_rc_ack()
80 case OP(RDMA_READ_RESPONSE_ONLY): in qib_make_rc_ack()
87 case OP(ATOMIC_ACKNOWLEDGE): in qib_make_rc_ack()
96 case OP(SEND_ONLY): in qib_make_rc_ack()
97 case OP(ACKNOWLEDGE): in qib_make_rc_ack()
106 if (e->opcode == OP(RDMA_READ_REQUEST)) { in qib_make_rc_ack()
127 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST); in qib_make_rc_ack()
129 qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY); in qib_make_rc_ack()
140 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE); in qib_make_rc_ack()
[all …]
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| /drivers/infiniband/hw/hfi1/ |
| D | uc.c | 11 #define OP(x) UC_OP(x) macro
122 qp->s_state = OP(SEND_FIRST); in hfi1_make_uc_req()
127 qp->s_state = OP(SEND_ONLY); in hfi1_make_uc_req()
130 OP(SEND_ONLY_WITH_IMMEDIATE); in hfi1_make_uc_req()
151 qp->s_state = OP(RDMA_WRITE_FIRST); in hfi1_make_uc_req()
156 qp->s_state = OP(RDMA_WRITE_ONLY); in hfi1_make_uc_req()
159 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE); in hfi1_make_uc_req()
176 case OP(SEND_FIRST): in hfi1_make_uc_req()
177 qp->s_state = OP(SEND_MIDDLE); in hfi1_make_uc_req()
179 case OP(SEND_MIDDLE): in hfi1_make_uc_req()
[all …]
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| D | trace.c | 102 #define OP(transport, op) IB_OPCODE_## transport ## _ ## op macro
263 case OP(RC, SEND_LAST_WITH_IMMEDIATE): in parse_everbs_hdrs()
264 case OP(UC, SEND_LAST_WITH_IMMEDIATE): in parse_everbs_hdrs()
265 case OP(RC, SEND_ONLY_WITH_IMMEDIATE): in parse_everbs_hdrs()
266 case OP(UC, SEND_ONLY_WITH_IMMEDIATE): in parse_everbs_hdrs()
267 case OP(RC, RDMA_WRITE_LAST_WITH_IMMEDIATE): in parse_everbs_hdrs()
268 case OP(UC, RDMA_WRITE_LAST_WITH_IMMEDIATE): in parse_everbs_hdrs()
273 case OP(RC, RDMA_WRITE_ONLY_WITH_IMMEDIATE): in parse_everbs_hdrs()
274 case OP(UC, RDMA_WRITE_ONLY_WITH_IMMEDIATE): in parse_everbs_hdrs()
282 case OP(RC, RDMA_READ_REQUEST): in parse_everbs_hdrs()
[all …]
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| D | rc.c | 98 case OP(RDMA_READ_RESPONSE_LAST): in make_rc_ack()
99 case OP(RDMA_READ_RESPONSE_ONLY): in make_rc_ack()
103 case OP(ATOMIC_ACKNOWLEDGE): in make_rc_ack()
122 case OP(SEND_ONLY): in make_rc_ack()
123 case OP(ACKNOWLEDGE): in make_rc_ack()
138 if (e->opcode == OP(RDMA_READ_REQUEST)) { in make_rc_ack()
163 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST); in make_rc_ack()
165 qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY); in make_rc_ack()
215 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE); in make_rc_ack()
226 case OP(RDMA_READ_RESPONSE_FIRST): in make_rc_ack()
[all …]
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| D | rc.h | 11 #define OP(x) IB_OPCODE_RC_##x macro
22 qp->s_ack_state = OP(ACKNOWLEDGE); in update_ack_queue()
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| D | tid_rdma.c | 2192 qp->s_ack_state = OP(ACKNOWLEDGE); in tid_rdma_rcv_error()
5478 e->opcode == OP(RDMA_READ_REQUEST)) && in hfi1_tid_rdma_ack_interlock()
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| /drivers/tee/optee/ |
| D | Kconfig | 2 # OP-TEE Trusted Execution Environment Configuration
4 tristate "OP-TEE"
8 This implements the OP-TEE Trusted Execution Environment (TEE)
17 used by OP-TEE TEE driver.
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| /drivers/pinctrl/cirrus/ |
| D | pinctrl-lochnagar.c | 437 #define LN_FUNC(NAME, TYPE, OP) \ argument
438 { .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP }
440 #define LN_FUNC_PIN(REV, ID, OP) \ argument
441 LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP)
443 #define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP) argument
444 #define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP) argument
446 #define LN_FUNC_AIF(REV, ID, OP) \ argument
447 LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP)
449 #define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP) argument
450 #define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP) argument
[all …]
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| /drivers/gpu/drm/v3d/ |
| D | v3d_drv.h | 310 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ argument
317 OP; \
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| /drivers/gpu/drm/i915/ |
| D | i915_utils.h | 316 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ argument
323 OP; \
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| /drivers/gpu/drm/vc4/ |
| D | vc4_drv.h | 782 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ argument
789 OP; \
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| /drivers/char/hw_random/ |
| D | Kconfig | 470 tristate "OP-TEE based Random Number Generator support"
474 This driver provides support for OP-TEE based Random Number
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| /drivers/net/ethernet/qlogic/qed/ |
| D | qed_debug.c | 2851 SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD); in qed_grc_dump_vfc_cam()
2898 SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD); in qed_grc_dump_vfc_ram()
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