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Searched refs:PACKET3_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_enums.h175 #define PACKET3_CLEAR_STATE 0x12 macro
Dsoc15d.h84 #define PACKET3_CLEAR_STATE 0x12 macro
Dnvd.h59 #define PACKET3_CLEAR_STATE 0x12 macro
Dvid.h116 #define PACKET3_CLEAR_STATE 0x12 macro
Dcikd.h234 #define PACKET3_CLEAR_STATE 0x12 macro
Dsid.h1670 #define PACKET3_CLEAR_STATE 0x12 macro
Dgfx_v6_0.c2073 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start()
2913 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_get_csb_buffer()
Dgfx_v7_0.c2576 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_cp_gfx_start()
4043 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_get_csb_buffer()
Dgfx_v8_0.c1295 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
4231 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_cp_gfx_start()
Dgfx_v9_0.c1790 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_get_csb_buffer()
3301 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_cp_gfx_start()
Dgfx_v10_0.c4456 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_get_csb_buffer()
6283 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_cp_gfx_start()
6303 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_cp_gfx_start()
/drivers/gpu/drm/radeon/
Dnid.h1164 #define PACKET3_CLEAR_STATE 0x12 macro
Dsi.c3601 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3620 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
4540 case PACKET3_CLEAR_STATE: in si_vm_packet3_gfx_check()
4658 case PACKET3_CLEAR_STATE: in si_vm_packet3_compute_check()
5770 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in si_get_csb_buffer()
Dsid.h1607 #define PACKET3_CLEAR_STATE 0x12 macro
Dcikd.h1702 #define PACKET3_CLEAR_STATE 0x12 macro
Devergreen_cs.c1834 case PACKET3_CLEAR_STATE: in evergreen_packet3_check()
3364 case PACKET3_CLEAR_STATE: in evergreen_vm_packet3_check()
Devergreend.h1550 #define PACKET3_CLEAR_STATE 0x12 macro
Dni.c1575 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
Dcik.c4010 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
6760 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_get_csb_buffer()
Devergreen.c3038 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()