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Searched refs:PAUSE (Results 1 – 21 of 21) sorted by relevance

/drivers/net/ethernet/apple/
Dmace.c306 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); in dbdma_reset()
472 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_open()
482 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); in mace_open()
510 rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_close()
511 td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_close()
970 out_le32(&rd->control, (PAUSE << 16) | PAUSE); in mace_rxdma_intr()
Dbmac.c182 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD)); in dbdma_continue()
190 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)); in dbdma_reset()
483 rd->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_suspend()
484 td->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_suspend()
1407 rd->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_close()
1408 td->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_close()
1497 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); in bmac_tx_timeout()
1503 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); in bmac_tx_timeout()
/drivers/accessibility/speakup/
Dspeakup_soft.c38 { PAUSE, .u.n = {"\x01P" } },
166 var->var_id != PAUSE && var->var_id != DIRECT) { in get_initstring()
Dspeakup_dummy.c24 { PAUSE, .u.s = {"PAUSE\n"} },
Dspk_types.h50 DIRECT, PAUSE, enumerator
Dvarhandlers.c50 { "pause", PAUSE, VAR_STRING, spk_str_pause, NULL },
/drivers/scsi/
Dmac53c94.c114 writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control); in DEF_SCSI_QCMD()
140 writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control); in mac53c94_init()
Dmesh.c367 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_init()
1723 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_host_reset()
/drivers/clk/samsung/
Dclk-exynos5260.h322 #define PAUSE 0x1004 macro
Dclk-exynos5433.c971 #define PAUSE 0x1008 macro
1035 PAUSE,
/drivers/dma/
Dhisi_dma.c49 PAUSE, enumerator
/drivers/scsi/aic7xxx/
Daic79xx_pci.c451 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); in ahd_pci_test_register_access()
Daic7xxx_reg.h_shipped629 #define PAUSE 0x04
Daic7xxx_pci.c1212 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); in ahc_pci_test_register_access()
Daic79xx_reg.h_shipped443 #define PAUSE 0x04
Daic7xxx.reg830 field PAUSE 0x04
Daic7xxx_core.c321 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); in ahc_is_paused()
4433 ahc->pause = ahc->unpause | PAUSE; in ahc_softc_init()
Daic79xx_core.c351 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0); in ahd_is_paused()
6092 ahd->pause = PAUSE; in ahd_softc_init()
Daic79xx.reg269 field PAUSE 0x04
/drivers/ata/
Dpata_macio.c584 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control); in pata_macio_freeze()
/drivers/block/
Dswim3.c752 out_le32(&dr->control, (RUN | PAUSE) << 16); in swim3_interrupt()