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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 19 of 19) sorted by relevance

/drivers/pinctrl/renesas/
Dpfc-r8a77470.c2767 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2795 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2823 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2851 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2880 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2908 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2936 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2964 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2992 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
3020 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
[all …]
Dpfc-sh7734.c1825 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1862 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1898 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1935 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1973 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2009 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2051 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2096 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2133 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2171 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
[all …]
Dpfc-r8a7790.c5236 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5273 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5311 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5341 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5375 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5409 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5447 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5484 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5520 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5562 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-emev2.c1609 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1629 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1643 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1657 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1683 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1704 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
Dpfc-r8a7778.c2261 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2317 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2362 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2415 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2458 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2502 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2548 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2600 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2640 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2681 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7779.c3379 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3418 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3457 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3504 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3556 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3605 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3652 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3691 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3729 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3773 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7794.c4919 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4974 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5015 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5051 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5093 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5129 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5166 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5213 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5251 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5287 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7791.c5758 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5818 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5855 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5892 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5931 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5976 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
6015 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
6056 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6098 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6142 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7792.c2418 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2477 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2536 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2585 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2632 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2674 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2715 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2758 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Dsh_pfc.h170 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ macro
759 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
Dpfc-r8a77995.c2785 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2818 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a77950.c5212 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5240 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5268 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a7796.c5647 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5673 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5701 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77965.c5904 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5930 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5958 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77951.c5692 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5718 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5746 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77990.c5047 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5076 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a77970.c2454 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Dpfc-r8a77980.c2896 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Dpfc-r8a779a0.c3709 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,