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Searched refs:R9 (Results 1 – 15 of 15) sorted by relevance

/drivers/media/i2c/
Dwm8739.c36 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator
127 wm8739_write(sd, R9, 0x000); in wm8739_s_clock_freq()
145 wm8739_write(sd, R9, 0x001); in wm8739_s_clock_freq()
231 wm8739_write(sd, R9, 0x001); in wm8739_probe()
/drivers/tty/serial/
Dsunzilog.c1340 write_zsreg(channel, R9, FHWRES); in sunzilog_init_hw()
1353 up->curregs[R9] = NV; in sunzilog_init_hw()
1358 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1359 write_zsreg(channel, R9, up->curregs[R9]); in sunzilog_init_hw()
1369 up->curregs[R9] = NV; in sunzilog_init_hw()
1384 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1385 write_zsreg(channel, R9, up->curregs[R9]); in sunzilog_init_hw()
1593 up->curregs[R9] |= MIE; in sunzilog_init()
1594 write_zsreg(channel, R9, up->curregs[R9]); in sunzilog_init()
1630 up->curregs[R9] &= ~MIE; in sunzilog_exit()
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Dzs.h69 #define R9 9 macro
Dsunzilog.h40 #define R9 9 macro
Dip22zilog.h48 #define R9 9 macro
Dip22zilog.c703 write_zsreg(channel, R9, FHWRES); in __ip22zilog_reset()
721 write_zsreg(channel, R9, up->curregs[R9]); in __ip22zilog_startup()
1144 up->curregs[R9] = NV | MIE; in ip22zilog_prepare()
Dpmac_zilog.h136 #define R9 9 macro
Dpmac_zilog.c180 write_zsreg(uap, R9, regs[R9]); in pmz_load_zsregs()
842 uap->curregs[R9] = 0; in __pmz_startup()
870 uap->curregs[R9] |= NV | MIE; in __pmz_startup()
Dzs.c272 write_zsreg(zport, R9, regs[9]); in load_zsregs()
839 write_zsreg(zport, R9, FHWRES); in zs_reset()
841 write_zsreg(zport, R9, 0); in zs_reset()
/drivers/net/hamradio/
Dz8530.h16 #define R9 9 macro
Ddmascc.c283 write_scc(&info->priv[0], R9, FHWRES); in dmascc_exit()
486 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
603 write_scc(&info->priv[0], R9, FHWRES); in setup_adapter()
750 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
872 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
Dscc.c807 wr(scc,R9,VIS); /* vector includes status */ in init_channel()
882 or(scc,R9,MIE); /* master interrupt enable */ in init_channel()
1500 OutReg(scc->ctrl,R9,FHWRES); /* force hardware reset */ in z8530_init()
1503 wr(scc, R9, VIS); /* vector includes status */ in z8530_init()
1767 OutReg(hwcfg.ctrl_a, R9, FHWRES); in scc_net_siocdevprivate()
2138 OutReg(ctrl,R9,FHWRES); /* force hardware reset */ in scc_cleanup_driver()
/drivers/memory/
Djedec_ddr.h41 #define R9 9 macro
/drivers/net/wan/
Dz85230.h35 #define R9 9 macro
Dz85230.c1148 write_zsreg(&dev->chanA, R9, 0xC0); in do_z8530_init()
1248 write_zsreg(&dev->chanA, R9, 0xC0); in z8530_shutdown()