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Searched refs:RB_BUFSZ (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c887 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
1059 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
1973 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); in vcn_v2_0_start_sriov()
Dvcn_v2_5.c872 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
1064 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1283 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
Duvd_v5_0.c417 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
Dvcn_v3_0.c1061 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start_dpg_mode()
1248 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start()
1435 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); in vcn_v3_0_start_sriov()
Dvcn_v1_0.c908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
Duvd_v7_0.c921 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); in uvd_v7_0_sriov_start()
1088 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v7_0_start()
Duvd_v6_0.c842 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
Dsid.h1275 #define RB_BUFSZ(x) ((x) << 0) macro
Dgfx_v10_0.c6386 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6429 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6672 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_gfx_mqd_init()
Dgfx_v8_0.c4294 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
Dgfx_v9_0.c3336 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
/drivers/gpu/drm/radeon/
Drv770d.h350 #define RB_BUFSZ(x) ((x) << 0) macro
Dnid.h485 #define RB_BUFSZ(x) ((x) << 0) macro
Dsid.h1247 #define RB_BUFSZ(x) ((x) << 0) macro
Dcikd.h1303 #define RB_BUFSZ(x) ((x) << 0) macro
Drv770.c1112 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
Devergreend.h477 #define RB_BUFSZ(x) ((x) << 0) macro
Dr600d.h196 #define RB_BUFSZ(x) ((x) << 0) macro
Dr600.c2658 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
Devergreen.c2979 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()