Searched refs:REG_FIELD_MASK (Results 1 – 4 of 4) sorted by relevance
/drivers/gpu/drm/amd/amdgpu/ |
D | mxgpu_vi.c | 321 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_send_ack() 368 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_rcv_msg() 390 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); in xgpu_vi_poll_ack()
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D | amdgpu.h | 1223 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK macro 1226 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1227 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1230 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1233 …WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, fi… 1236 …WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_F…
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D | soc15_common.h | 45 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ 180 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
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/drivers/misc/habanalabs/common/ |
D | habanalabs.h | 2040 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK macro 2043 ~REG_FIELD_MASK(reg, field)) | \
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