/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_opp.c | 92 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator() 97 REG_SET_2(DPG_OFFSET_SEGMENT, 0, in opp2_set_disp_pattern_generator() 171 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_set_disp_pattern_generator() 174 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_set_disp_pattern_generator() 177 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_set_disp_pattern_generator() 282 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator() 299 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_program_dpg_dimensions() 312 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_dpg_set_blank_color() 315 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_dpg_set_blank_color() 318 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_dpg_set_blank_color()
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D | dcn20_dpp_cm.c | 582 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp20_program_shaper_luta_settings() 585 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp20_program_shaper_luta_settings() 588 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp20_program_shaper_luta_settings() 592 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp20_program_shaper_luta_settings() 596 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp20_program_shaper_luta_settings() 600 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, in dpp20_program_shaper_luta_settings() 732 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, in dpp20_program_shaper_lutb_settings() 735 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, in dpp20_program_shaper_lutb_settings() 738 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, in dpp20_program_shaper_lutb_settings() 742 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, in dpp20_program_shaper_lutb_settings() [all …]
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D | dcn20_hubp.c | 74 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp2_set_vm_system_aperture_settings() 87 REG_SET_2(BLANK_OFFSET_0, 0, in hubp2_program_deadline() 97 REG_SET_2(DST_AFTER_SCALER, 0, in hubp2_program_deadline() 122 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp2_program_deadline() 144 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp2_program_deadline() 252 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp2_setup_interdependent() 259 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp2_setup_interdependent() 263 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp2_setup_interdependent() 276 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp2_setup_interdependent() 291 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp2_setup_interdependent() [all …]
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D | dcn20_optc.c | 129 REG_SET_2(OTG_GSL_WINDOW_X, 0, in optc2_set_gsl_window() 132 REG_SET_2(OTG_GSL_WINDOW_Y, 0, in optc2_set_gsl_window() 166 REG_SET_2(OTG_DSC_START_POSITION, 0, in optc2_set_dsc_encoder_frame_start() 516 REG_SET_2(OTG_CRC_CNTL2, 0, in optc2_configure_crc()
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D | dcn20_stream_encoder.c | 173 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc2_stream_encoder_stop_hdmi_info_packets() 183 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc2_stream_encoder_stop_hdmi_info_packets() 193 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc2_stream_encoder_stop_hdmi_info_packets() 203 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
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D | dcn20_dsc.c | 558 REG_SET_2(DSCCIF_CONFIG1, 0, in dsc_write_to_registers() 600 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers() 604 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers() 611 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers() 620 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers() 624 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers() 628 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
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D | dcn20_vmid.c | 85 REG_SET_2(CNTL, 0, in dcn20_vmid_setup()
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/drivers/gpu/drm/amd/display/dmub/src/ |
D | dmub_dcn30.c | 105 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn30_backdoor_load() 114 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn30_backdoor_load() 139 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows() 154 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows() 165 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows() 171 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows() 182 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows() 188 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows() 198 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn30_setup_windows()
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D | dmub_dcn20.c | 172 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn20_backdoor_load() 181 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn20_backdoor_load() 208 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows() 223 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows() 235 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows() 241 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows() 252 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows() 258 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows() 268 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn20_setup_windows()
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D | dmub_dcn31.c | 159 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, in dmub_dcn31_backdoor_load() 168 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, in dmub_dcn31_backdoor_load() 190 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows() 199 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows() 208 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows() 214 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows() 224 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, in dmub_dcn31_setup_windows()
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/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_dpp_dscl.c | 107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0, in dpp1_dscl_set_overscan() 111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0, in dpp1_dscl_set_overscan() 124 REG_SET_2(OTG_H_BLANK, 0, in dpp1_dscl_set_otg_blank() 128 REG_SET_2(OTG_V_BLANK, 0, in dpp1_dscl_set_otg_blank() 239 REG_SET_2(LB_DATA_FORMAT, 0, in dpp1_dscl_set_lb() 247 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb() 405 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter() 580 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale() 585 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale() 622 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init() [all …]
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D | dcn10_hubp.c | 594 REG_SET_2(BLANK_OFFSET_0, 0, in hubp1_program_deadline() 604 REG_SET_2(DST_AFTER_SCALER, 0, in hubp1_program_deadline() 629 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp1_program_deadline() 651 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp1_program_deadline() 696 REG_SET_2(PREFETCH_SETTINS, 0, in hubp1_setup_interdependent() 703 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp1_setup_interdependent() 713 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp1_setup_interdependent() 726 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp1_setup_interdependent() 773 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_system_aperture_settings() 813 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_context0_settings() [all …]
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D | dcn10_cm_common.c | 56 REG_SET_2(cur_csc_reg, 0, in cm_helper_program_color_matrices() 73 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_xfer_func() 76 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_xfer_func() 79 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_xfer_func() 92 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_xfer_func() 98 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_xfer_func() 104 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_xfer_func()
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D | dcn10_optc.c | 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, in optc1_program_global_sync() 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, in optc1_disable_stereo() 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, in optc1_setup_vertical_interrupt0() 879 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, in optc1_set_static_screen_control() 1133 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern() 1145 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
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/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_opp.c | 369 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping() 377 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping() 382 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping() 387 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping() 393 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping() 398 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, in dce110_opp_set_clamping() 402 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, in dce110_opp_set_clamping() 406 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, in dce110_opp_set_clamping() 429 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping() 437 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce60_opp_set_clamping() [all …]
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D | dce_transform.c | 131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration() 164 REG_SET_2(SCL_TAP_CONTROL, 0, in dce60_setup_scaling_configuration() 199 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, in program_overscan() 202 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, in program_overscan() 266 REG_SET_2(VIEWPORT_START, 0, in program_viewport() 270 REG_SET_2(VIEWPORT_SIZE, 0, in program_viewport() 350 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in program_scl_ratios_inits() 354 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in program_scl_ratios_inits() 374 REG_SET_2(SCL_HORZ_FILTER_INIT_RGB_LUMA, 0, in dce60_program_scl_ratios_inits() 379 REG_SET_2(SCL_HORZ_FILTER_INIT_CHROMA, 0, in dce60_program_scl_ratios_inits() [all …]
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D | dce_ipp.c | 57 REG_SET_2(CUR_POSITION, 0, in dce_ipp_cursor_set_position() 61 REG_SET_2(CUR_HOT_SPOT, 0, in dce_ipp_cursor_set_position() 119 REG_SET_2(CUR_SIZE, 0, in dce_ipp_cursor_set_attributes() 149 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, in dce_ipp_program_prescale() 153 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, in dce_ipp_program_prescale() 157 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, in dce_ipp_program_prescale() 244 REG_SET_2(DEGAMMA_CONTROL, 0, in dce60_ipp_set_degamma()
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D | dce_mem_input.c | 172 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in program_urgency_watermark() 187 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce60_program_urgency_watermark() 202 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce120_program_urgency_watermark() 206 REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, in dce120_program_urgency_watermark() 576 REG_SET_2(GRPH_SWAP_CNTL, 0, in program_grph_pixel_format() 805 REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, in program_sec_addr()
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D | dce_hwseq.c | 71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock() 76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
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/drivers/gpu/drm/amd/display/dc/dcn21/ |
D | dcn21_hubbub.c | 163 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub21_program_urgent_watermarks() 208 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub21_program_urgent_watermarks() 253 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub21_program_urgent_watermarks() 298 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub21_program_urgent_watermarks() 359 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks() 376 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks() 394 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks() 411 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks() 429 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks() 446 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks() [all …]
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D | dcn21_hubp.c | 193 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport() 197 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, in hubp21_set_viewport() 202 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, in hubp21_set_viewport() 206 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, in hubp21_set_viewport() 211 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport() 215 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, in hubp21_set_viewport() 219 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, in hubp21_set_viewport() 223 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, in hubp21_set_viewport() 246 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp21_set_vm_system_aperture_settings()
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/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_dpp.c | 166 REG_SET_2(PRE_DEGAM, 0, in dpp3_set_pre_degam() 193 REG_SET_2(FORMAT_CONTROL, 0, in dpp3_cnv_setup() 305 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup() 314 REG_SET_2(PRE_DEALPHA, 0, in dpp3_cnv_setup() 317 REG_SET_2(PRE_REALPHA, 0, in dpp3_cnv_setup() 816 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp3_program_shaper_luta_settings() 819 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp3_program_shaper_luta_settings() 822 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp3_program_shaper_luta_settings() 826 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp3_program_shaper_luta_settings() 830 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp3_program_shaper_luta_settings() [all …]
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D | dcn30_dio_stream_encoder.c | 243 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc3_stream_encoder_stop_hdmi_info_packets() 253 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc3_stream_encoder_stop_hdmi_info_packets() 263 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc3_stream_encoder_stop_hdmi_info_packets() 273 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc3_stream_encoder_stop_hdmi_info_packets() 283 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0, in enc3_stream_encoder_stop_hdmi_info_packets() 293 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0, in enc3_stream_encoder_stop_hdmi_info_packets() 303 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0, in enc3_stream_encoder_stop_hdmi_info_packets() 308 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
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D | dcn30_mpc.c | 484 REG_SET_2(SHAPER_RAMA_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings() 487 REG_SET_2(SHAPER_RAMA_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings() 490 REG_SET_2(SHAPER_RAMA_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings() 494 REG_SET_2(SHAPER_RAMA_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_luta_settings() 497 REG_SET_2(SHAPER_RAMA_END_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_luta_settings() 500 REG_SET_2(SHAPER_RAMA_END_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_luta_settings() 633 REG_SET_2(SHAPER_RAMB_START_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings() 636 REG_SET_2(SHAPER_RAMB_START_CNTL_G[rmu_idx], 0, in mpc3_program_shaper_lutb_settings() 639 REG_SET_2(SHAPER_RAMB_START_CNTL_R[rmu_idx], 0, in mpc3_program_shaper_lutb_settings() 643 REG_SET_2(SHAPER_RAMB_END_CNTL_B[rmu_idx], 0, in mpc3_program_shaper_lutb_settings() [all …]
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D | dcn30_cm_common.c | 51 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_gamcor_xfer_func() 54 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_gamcor_xfer_func() 57 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_gamcor_xfer_func() 75 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_gamcor_xfer_func() 78 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_gamcor_xfer_func() 81 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_gamcor_xfer_func()
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