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Searched refs:RING_START (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/i810/
Di810_drv.h202 #define RING_START 0x08 macro
/drivers/gpu/drm/i915/gt/
Dintel_ring_submission.c213 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
260 ENGINE_READ(engine, RING_START), in xcs_resume()
328 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
337 ENGINE_READ_FW(engine, RING_START)); in reset_prepare()
Dselftest_lrc.c265 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
400 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
1482 *cs++ = i915_mmio_reg_offset(RING_START(0)); in emit_indirect_ctx_bb_canary()
Dintel_gt.c166 intel_uncore_write(uncore, RING_START(base), 0); in init_unused_ring()
Dintel_engine_cs.c1481 ENGINE_READ(engine, RING_START)); in intel_engine_print_registers()
Dintel_execlists_submission.c1965 ENGINE_READ(engine, RING_START), in process_csb()
/drivers/gpu/drm/i915/
Di915_request.c2030 u32 ring = ENGINE_READ(engine, RING_START); in engine_match_ring()
Di915_gpu_error.c1163 ee->start = ENGINE_READ(engine, RING_START); in engine_record_registers()
Di915_reg.h2530 #define RING_START(base) _MMIO((base) + 0x38) macro
/drivers/gpu/drm/i915/gvt/
Dscheduler.c651 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = in update_vreg_in_ctx()
Dhandlers.c2228 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); in init_generic_mmio_info()