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Searched refs:SDMA1_HWIP (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dcyan_skillfish_reg_init.c47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in cyan_skillfish_reg_base_init()
Dnavi12_reg_init.c46 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi12_reg_base_init()
Dnavi10_reg_init.c46 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi10_reg_base_init()
Dnavi14_reg_init.c46 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi14_reg_base_init()
Dbeige_goby_reg_init.c47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in beige_goby_reg_base_init()
Dsienna_cichlid_reg_init.c47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init()
Ddimgrey_cavefish_reg_init.c47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
Daldebaran_reg_init.c44 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); in aldebaran_reg_base_init()
Darct_reg_init.c45 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); in arct_reg_base_init()
Dvega10_reg_init.c48 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); in vega10_reg_base_init()
Dvega20_reg_init.c47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); in vega20_reg_base_init()
Damdgpu_discovery.c115 [SDMA1_HWIP] = SDMA1_HWID,
Damdgpu.h732 SDMA1_HWIP, enumerator
Dsdma_v4_0.c401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()