1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 */
5
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/cpu_pm.h>
10 #include <linux/delay.h>
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/slab.h>
20 #include <linux/sys_soc.h>
21 #include <linux/timekeeping.h>
22 #include <linux/iopoll.h>
23
24 #include <linux/platform_data/ti-sysc.h>
25
26 #include <dt-bindings/bus/ti-sysc.h>
27
28 #define DIS_ISP BIT(2)
29 #define DIS_IVA BIT(1)
30 #define DIS_SGX BIT(0)
31
32 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
33
34 #define MAX_MODULE_SOFTRESET_WAIT 10000
35
36 enum sysc_soc {
37 SOC_UNKNOWN,
38 SOC_2420,
39 SOC_2430,
40 SOC_3430,
41 SOC_AM35,
42 SOC_3630,
43 SOC_4430,
44 SOC_4460,
45 SOC_4470,
46 SOC_5430,
47 SOC_AM3,
48 SOC_AM4,
49 SOC_DRA7,
50 };
51
52 struct sysc_address {
53 unsigned long base;
54 struct list_head node;
55 };
56
57 struct sysc_module {
58 struct sysc *ddata;
59 struct list_head node;
60 };
61
62 struct sysc_soc_info {
63 unsigned long general_purpose:1;
64 enum sysc_soc soc;
65 struct mutex list_lock; /* disabled and restored modules list lock */
66 struct list_head disabled_modules;
67 struct list_head restored_modules;
68 struct notifier_block nb;
69 };
70
71 enum sysc_clocks {
72 SYSC_FCK,
73 SYSC_ICK,
74 SYSC_OPTFCK0,
75 SYSC_OPTFCK1,
76 SYSC_OPTFCK2,
77 SYSC_OPTFCK3,
78 SYSC_OPTFCK4,
79 SYSC_OPTFCK5,
80 SYSC_OPTFCK6,
81 SYSC_OPTFCK7,
82 SYSC_MAX_CLOCKS,
83 };
84
85 static struct sysc_soc_info *sysc_soc;
86 static const char * const reg_names[] = { "rev", "sysc", "syss", };
87 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
88 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
89 "opt5", "opt6", "opt7",
90 };
91
92 #define SYSC_IDLEMODE_MASK 3
93 #define SYSC_CLOCKACTIVITY_MASK 3
94
95 /**
96 * struct sysc - TI sysc interconnect target module registers and capabilities
97 * @dev: struct device pointer
98 * @module_pa: physical address of the interconnect target module
99 * @module_size: size of the interconnect target module
100 * @module_va: virtual address of the interconnect target module
101 * @offsets: register offsets from module base
102 * @mdata: ti-sysc to hwmod translation data for a module
103 * @clocks: clocks used by the interconnect target module
104 * @clock_roles: clock role names for the found clocks
105 * @nr_clocks: number of clocks used by the interconnect target module
106 * @rsts: resets used by the interconnect target module
107 * @legacy_mode: configured for legacy mode if set
108 * @cap: interconnect target module capabilities
109 * @cfg: interconnect target module configuration
110 * @cookie: data used by legacy platform callbacks
111 * @name: name if available
112 * @revision: interconnect target module revision
113 * @reserved: target module is reserved and already in use
114 * @enabled: sysc runtime enabled status
115 * @needs_resume: runtime resume needed on resume from suspend
116 * @child_needs_resume: runtime resume needed for child on resume from suspend
117 * @disable_on_idle: status flag used for disabling modules with resets
118 * @idle_work: work structure used to perform delayed idle on a module
119 * @pre_reset_quirk: module specific pre-reset quirk
120 * @post_reset_quirk: module specific post-reset quirk
121 * @reset_done_quirk: module specific reset done quirk
122 * @module_enable_quirk: module specific enable quirk
123 * @module_disable_quirk: module specific disable quirk
124 * @module_unlock_quirk: module specific sysconfig unlock quirk
125 * @module_lock_quirk: module specific sysconfig lock quirk
126 */
127 struct sysc {
128 struct device *dev;
129 u64 module_pa;
130 u32 module_size;
131 void __iomem *module_va;
132 int offsets[SYSC_MAX_REGS];
133 struct ti_sysc_module_data *mdata;
134 struct clk **clocks;
135 const char **clock_roles;
136 int nr_clocks;
137 struct reset_control *rsts;
138 const char *legacy_mode;
139 const struct sysc_capabilities *cap;
140 struct sysc_config cfg;
141 struct ti_sysc_cookie cookie;
142 const char *name;
143 u32 revision;
144 unsigned int reserved:1;
145 unsigned int enabled:1;
146 unsigned int needs_resume:1;
147 unsigned int child_needs_resume:1;
148 struct delayed_work idle_work;
149 void (*pre_reset_quirk)(struct sysc *sysc);
150 void (*post_reset_quirk)(struct sysc *sysc);
151 void (*reset_done_quirk)(struct sysc *sysc);
152 void (*module_enable_quirk)(struct sysc *sysc);
153 void (*module_disable_quirk)(struct sysc *sysc);
154 void (*module_unlock_quirk)(struct sysc *sysc);
155 void (*module_lock_quirk)(struct sysc *sysc);
156 };
157
158 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
159 bool is_child);
160
sysc_write(struct sysc * ddata,int offset,u32 value)161 static void sysc_write(struct sysc *ddata, int offset, u32 value)
162 {
163 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
164 writew_relaxed(value & 0xffff, ddata->module_va + offset);
165
166 /* Only i2c revision has LO and HI register with stride of 4 */
167 if (ddata->offsets[SYSC_REVISION] >= 0 &&
168 offset == ddata->offsets[SYSC_REVISION]) {
169 u16 hi = value >> 16;
170
171 writew_relaxed(hi, ddata->module_va + offset + 4);
172 }
173
174 return;
175 }
176
177 writel_relaxed(value, ddata->module_va + offset);
178 }
179
sysc_read(struct sysc * ddata,int offset)180 static u32 sysc_read(struct sysc *ddata, int offset)
181 {
182 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
183 u32 val;
184
185 val = readw_relaxed(ddata->module_va + offset);
186
187 /* Only i2c revision has LO and HI register with stride of 4 */
188 if (ddata->offsets[SYSC_REVISION] >= 0 &&
189 offset == ddata->offsets[SYSC_REVISION]) {
190 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
191
192 val |= tmp << 16;
193 }
194
195 return val;
196 }
197
198 return readl_relaxed(ddata->module_va + offset);
199 }
200
sysc_opt_clks_needed(struct sysc * ddata)201 static bool sysc_opt_clks_needed(struct sysc *ddata)
202 {
203 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
204 }
205
sysc_read_revision(struct sysc * ddata)206 static u32 sysc_read_revision(struct sysc *ddata)
207 {
208 int offset = ddata->offsets[SYSC_REVISION];
209
210 if (offset < 0)
211 return 0;
212
213 return sysc_read(ddata, offset);
214 }
215
sysc_read_sysconfig(struct sysc * ddata)216 static u32 sysc_read_sysconfig(struct sysc *ddata)
217 {
218 int offset = ddata->offsets[SYSC_SYSCONFIG];
219
220 if (offset < 0)
221 return 0;
222
223 return sysc_read(ddata, offset);
224 }
225
sysc_read_sysstatus(struct sysc * ddata)226 static u32 sysc_read_sysstatus(struct sysc *ddata)
227 {
228 int offset = ddata->offsets[SYSC_SYSSTATUS];
229
230 if (offset < 0)
231 return 0;
232
233 return sysc_read(ddata, offset);
234 }
235
sysc_poll_reset_sysstatus(struct sysc * ddata)236 static int sysc_poll_reset_sysstatus(struct sysc *ddata)
237 {
238 int error, retries;
239 u32 syss_done, rstval;
240
241 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
242 syss_done = 0;
243 else
244 syss_done = ddata->cfg.syss_mask;
245
246 if (likely(!timekeeping_suspended)) {
247 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
248 rstval, (rstval & ddata->cfg.syss_mask) ==
249 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
250 } else {
251 retries = MAX_MODULE_SOFTRESET_WAIT;
252 while (retries--) {
253 rstval = sysc_read_sysstatus(ddata);
254 if ((rstval & ddata->cfg.syss_mask) == syss_done)
255 return 0;
256 udelay(2); /* Account for udelay flakeyness */
257 }
258 error = -ETIMEDOUT;
259 }
260
261 return error;
262 }
263
sysc_poll_reset_sysconfig(struct sysc * ddata)264 static int sysc_poll_reset_sysconfig(struct sysc *ddata)
265 {
266 int error, retries;
267 u32 sysc_mask, rstval;
268
269 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
270
271 if (likely(!timekeeping_suspended)) {
272 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
273 rstval, !(rstval & sysc_mask),
274 100, MAX_MODULE_SOFTRESET_WAIT);
275 } else {
276 retries = MAX_MODULE_SOFTRESET_WAIT;
277 while (retries--) {
278 rstval = sysc_read_sysconfig(ddata);
279 if (!(rstval & sysc_mask))
280 return 0;
281 udelay(2); /* Account for udelay flakeyness */
282 }
283 error = -ETIMEDOUT;
284 }
285
286 return error;
287 }
288
289 /* Poll on reset status */
sysc_wait_softreset(struct sysc * ddata)290 static int sysc_wait_softreset(struct sysc *ddata)
291 {
292 int syss_offset, error = 0;
293
294 if (ddata->cap->regbits->srst_shift < 0)
295 return 0;
296
297 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
298
299 if (syss_offset >= 0)
300 error = sysc_poll_reset_sysstatus(ddata);
301 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
302 error = sysc_poll_reset_sysconfig(ddata);
303
304 return error;
305 }
306
sysc_add_named_clock_from_child(struct sysc * ddata,const char * name,const char * optfck_name)307 static int sysc_add_named_clock_from_child(struct sysc *ddata,
308 const char *name,
309 const char *optfck_name)
310 {
311 struct device_node *np = ddata->dev->of_node;
312 struct device_node *child;
313 struct clk_lookup *cl;
314 struct clk *clock;
315 const char *n;
316
317 if (name)
318 n = name;
319 else
320 n = optfck_name;
321
322 /* Does the clock alias already exist? */
323 clock = of_clk_get_by_name(np, n);
324 if (!IS_ERR(clock)) {
325 clk_put(clock);
326
327 return 0;
328 }
329
330 child = of_get_next_available_child(np, NULL);
331 if (!child)
332 return -ENODEV;
333
334 clock = devm_get_clk_from_child(ddata->dev, child, name);
335 if (IS_ERR(clock))
336 return PTR_ERR(clock);
337
338 /*
339 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
340 * limit for clk_get(). If cl ever needs to be freed, it should be done
341 * with clkdev_drop().
342 */
343 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
344 if (!cl)
345 return -ENOMEM;
346
347 cl->con_id = n;
348 cl->dev_id = dev_name(ddata->dev);
349 cl->clk = clock;
350 clkdev_add(cl);
351
352 clk_put(clock);
353
354 return 0;
355 }
356
sysc_init_ext_opt_clock(struct sysc * ddata,const char * name)357 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
358 {
359 const char *optfck_name;
360 int error, index;
361
362 if (ddata->nr_clocks < SYSC_OPTFCK0)
363 index = SYSC_OPTFCK0;
364 else
365 index = ddata->nr_clocks;
366
367 if (name)
368 optfck_name = name;
369 else
370 optfck_name = clock_names[index];
371
372 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
373 if (error)
374 return error;
375
376 ddata->clock_roles[index] = optfck_name;
377 ddata->nr_clocks++;
378
379 return 0;
380 }
381
sysc_get_one_clock(struct sysc * ddata,const char * name)382 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
383 {
384 int error, i, index = -ENODEV;
385
386 if (!strncmp(clock_names[SYSC_FCK], name, 3))
387 index = SYSC_FCK;
388 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
389 index = SYSC_ICK;
390
391 if (index < 0) {
392 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
393 if (!ddata->clocks[i]) {
394 index = i;
395 break;
396 }
397 }
398 }
399
400 if (index < 0) {
401 dev_err(ddata->dev, "clock %s not added\n", name);
402 return index;
403 }
404
405 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
406 if (IS_ERR(ddata->clocks[index])) {
407 dev_err(ddata->dev, "clock get error for %s: %li\n",
408 name, PTR_ERR(ddata->clocks[index]));
409
410 return PTR_ERR(ddata->clocks[index]);
411 }
412
413 error = clk_prepare(ddata->clocks[index]);
414 if (error) {
415 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
416 name, error);
417
418 return error;
419 }
420
421 return 0;
422 }
423
sysc_get_clocks(struct sysc * ddata)424 static int sysc_get_clocks(struct sysc *ddata)
425 {
426 struct device_node *np = ddata->dev->of_node;
427 struct property *prop;
428 const char *name;
429 int nr_fck = 0, nr_ick = 0, i, error = 0;
430
431 ddata->clock_roles = devm_kcalloc(ddata->dev,
432 SYSC_MAX_CLOCKS,
433 sizeof(*ddata->clock_roles),
434 GFP_KERNEL);
435 if (!ddata->clock_roles)
436 return -ENOMEM;
437
438 of_property_for_each_string(np, "clock-names", prop, name) {
439 if (!strncmp(clock_names[SYSC_FCK], name, 3))
440 nr_fck++;
441 if (!strncmp(clock_names[SYSC_ICK], name, 3))
442 nr_ick++;
443 ddata->clock_roles[ddata->nr_clocks] = name;
444 ddata->nr_clocks++;
445 }
446
447 if (ddata->nr_clocks < 1)
448 return 0;
449
450 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
451 error = sysc_init_ext_opt_clock(ddata, NULL);
452 if (error)
453 return error;
454 }
455
456 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
457 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
458
459 return -EINVAL;
460 }
461
462 if (nr_fck > 1 || nr_ick > 1) {
463 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
464
465 return -EINVAL;
466 }
467
468 /* Always add a slot for main clocks fck and ick even if unused */
469 if (!nr_fck)
470 ddata->nr_clocks++;
471 if (!nr_ick)
472 ddata->nr_clocks++;
473
474 ddata->clocks = devm_kcalloc(ddata->dev,
475 ddata->nr_clocks, sizeof(*ddata->clocks),
476 GFP_KERNEL);
477 if (!ddata->clocks)
478 return -ENOMEM;
479
480 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
481 const char *name = ddata->clock_roles[i];
482
483 if (!name)
484 continue;
485
486 error = sysc_get_one_clock(ddata, name);
487 if (error)
488 return error;
489 }
490
491 return 0;
492 }
493
sysc_enable_main_clocks(struct sysc * ddata)494 static int sysc_enable_main_clocks(struct sysc *ddata)
495 {
496 struct clk *clock;
497 int i, error;
498
499 if (!ddata->clocks)
500 return 0;
501
502 for (i = 0; i < SYSC_OPTFCK0; i++) {
503 clock = ddata->clocks[i];
504
505 /* Main clocks may not have ick */
506 if (IS_ERR_OR_NULL(clock))
507 continue;
508
509 error = clk_enable(clock);
510 if (error)
511 goto err_disable;
512 }
513
514 return 0;
515
516 err_disable:
517 for (i--; i >= 0; i--) {
518 clock = ddata->clocks[i];
519
520 /* Main clocks may not have ick */
521 if (IS_ERR_OR_NULL(clock))
522 continue;
523
524 clk_disable(clock);
525 }
526
527 return error;
528 }
529
sysc_disable_main_clocks(struct sysc * ddata)530 static void sysc_disable_main_clocks(struct sysc *ddata)
531 {
532 struct clk *clock;
533 int i;
534
535 if (!ddata->clocks)
536 return;
537
538 for (i = 0; i < SYSC_OPTFCK0; i++) {
539 clock = ddata->clocks[i];
540 if (IS_ERR_OR_NULL(clock))
541 continue;
542
543 clk_disable(clock);
544 }
545 }
546
sysc_enable_opt_clocks(struct sysc * ddata)547 static int sysc_enable_opt_clocks(struct sysc *ddata)
548 {
549 struct clk *clock;
550 int i, error;
551
552 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
553 return 0;
554
555 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
556 clock = ddata->clocks[i];
557
558 /* Assume no holes for opt clocks */
559 if (IS_ERR_OR_NULL(clock))
560 return 0;
561
562 error = clk_enable(clock);
563 if (error)
564 goto err_disable;
565 }
566
567 return 0;
568
569 err_disable:
570 for (i--; i >= 0; i--) {
571 clock = ddata->clocks[i];
572 if (IS_ERR_OR_NULL(clock))
573 continue;
574
575 clk_disable(clock);
576 }
577
578 return error;
579 }
580
sysc_disable_opt_clocks(struct sysc * ddata)581 static void sysc_disable_opt_clocks(struct sysc *ddata)
582 {
583 struct clk *clock;
584 int i;
585
586 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
587 return;
588
589 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
590 clock = ddata->clocks[i];
591
592 /* Assume no holes for opt clocks */
593 if (IS_ERR_OR_NULL(clock))
594 return;
595
596 clk_disable(clock);
597 }
598 }
599
sysc_clkdm_deny_idle(struct sysc * ddata)600 static void sysc_clkdm_deny_idle(struct sysc *ddata)
601 {
602 struct ti_sysc_platform_data *pdata;
603
604 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
605 return;
606
607 pdata = dev_get_platdata(ddata->dev);
608 if (pdata && pdata->clkdm_deny_idle)
609 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
610 }
611
sysc_clkdm_allow_idle(struct sysc * ddata)612 static void sysc_clkdm_allow_idle(struct sysc *ddata)
613 {
614 struct ti_sysc_platform_data *pdata;
615
616 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
617 return;
618
619 pdata = dev_get_platdata(ddata->dev);
620 if (pdata && pdata->clkdm_allow_idle)
621 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
622 }
623
624 /**
625 * sysc_init_resets - init rstctrl reset line if configured
626 * @ddata: device driver data
627 *
628 * See sysc_rstctrl_reset_deassert().
629 */
sysc_init_resets(struct sysc * ddata)630 static int sysc_init_resets(struct sysc *ddata)
631 {
632 ddata->rsts =
633 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
634
635 return PTR_ERR_OR_ZERO(ddata->rsts);
636 }
637
638 /**
639 * sysc_parse_and_check_child_range - parses module IO region from ranges
640 * @ddata: device driver data
641 *
642 * In general we only need rev, syss, and sysc registers and not the whole
643 * module range. But we do want the offsets for these registers from the
644 * module base. This allows us to check them against the legacy hwmod
645 * platform data. Let's also check the ranges are configured properly.
646 */
sysc_parse_and_check_child_range(struct sysc * ddata)647 static int sysc_parse_and_check_child_range(struct sysc *ddata)
648 {
649 struct device_node *np = ddata->dev->of_node;
650 const __be32 *ranges;
651 u32 nr_addr, nr_size;
652 int len, error;
653
654 ranges = of_get_property(np, "ranges", &len);
655 if (!ranges) {
656 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
657
658 return -ENOENT;
659 }
660
661 len /= sizeof(*ranges);
662
663 if (len < 3) {
664 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
665
666 return -EINVAL;
667 }
668
669 error = of_property_read_u32(np, "#address-cells", &nr_addr);
670 if (error)
671 return -ENOENT;
672
673 error = of_property_read_u32(np, "#size-cells", &nr_size);
674 if (error)
675 return -ENOENT;
676
677 if (nr_addr != 1 || nr_size != 1) {
678 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
679
680 return -EINVAL;
681 }
682
683 ranges++;
684 ddata->module_pa = of_translate_address(np, ranges++);
685 ddata->module_size = be32_to_cpup(ranges);
686
687 return 0;
688 }
689
690 /* Interconnect instances to probe before l4_per instances */
691 static struct resource early_bus_ranges[] = {
692 /* am3/4 l4_wkup */
693 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
694 /* omap4/5 and dra7 l4_cfg */
695 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
696 /* omap4 l4_wkup */
697 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
698 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
699 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
700 };
701
702 static atomic_t sysc_defer = ATOMIC_INIT(10);
703
704 /**
705 * sysc_defer_non_critical - defer non_critical interconnect probing
706 * @ddata: device driver data
707 *
708 * We want to probe l4_cfg and l4_wkup interconnect instances before any
709 * l4_per instances as l4_per instances depend on resources on l4_cfg and
710 * l4_wkup interconnects.
711 */
sysc_defer_non_critical(struct sysc * ddata)712 static int sysc_defer_non_critical(struct sysc *ddata)
713 {
714 struct resource *res;
715 int i;
716
717 if (!atomic_read(&sysc_defer))
718 return 0;
719
720 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
721 res = &early_bus_ranges[i];
722 if (ddata->module_pa >= res->start &&
723 ddata->module_pa <= res->end) {
724 atomic_set(&sysc_defer, 0);
725
726 return 0;
727 }
728 }
729
730 atomic_dec_if_positive(&sysc_defer);
731
732 return -EPROBE_DEFER;
733 }
734
735 static struct device_node *stdout_path;
736
sysc_init_stdout_path(struct sysc * ddata)737 static void sysc_init_stdout_path(struct sysc *ddata)
738 {
739 struct device_node *np = NULL;
740 const char *uart;
741
742 if (IS_ERR(stdout_path))
743 return;
744
745 if (stdout_path)
746 return;
747
748 np = of_find_node_by_path("/chosen");
749 if (!np)
750 goto err;
751
752 uart = of_get_property(np, "stdout-path", NULL);
753 if (!uart)
754 goto err;
755
756 np = of_find_node_by_path(uart);
757 if (!np)
758 goto err;
759
760 stdout_path = np;
761
762 return;
763
764 err:
765 stdout_path = ERR_PTR(-ENODEV);
766 }
767
sysc_check_quirk_stdout(struct sysc * ddata,struct device_node * np)768 static void sysc_check_quirk_stdout(struct sysc *ddata,
769 struct device_node *np)
770 {
771 sysc_init_stdout_path(ddata);
772 if (np != stdout_path)
773 return;
774
775 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
776 SYSC_QUIRK_NO_RESET_ON_INIT;
777 }
778
779 /**
780 * sysc_check_one_child - check child configuration
781 * @ddata: device driver data
782 * @np: child device node
783 *
784 * Let's avoid messy situations where we have new interconnect target
785 * node but children have "ti,hwmods". These belong to the interconnect
786 * target node and are managed by this driver.
787 */
sysc_check_one_child(struct sysc * ddata,struct device_node * np)788 static void sysc_check_one_child(struct sysc *ddata,
789 struct device_node *np)
790 {
791 const char *name;
792
793 name = of_get_property(np, "ti,hwmods", NULL);
794 if (name && !of_device_is_compatible(np, "ti,sysc"))
795 dev_warn(ddata->dev, "really a child ti,hwmods property?");
796
797 sysc_check_quirk_stdout(ddata, np);
798 sysc_parse_dts_quirks(ddata, np, true);
799 }
800
sysc_check_children(struct sysc * ddata)801 static void sysc_check_children(struct sysc *ddata)
802 {
803 struct device_node *child;
804
805 for_each_child_of_node(ddata->dev->of_node, child)
806 sysc_check_one_child(ddata, child);
807 }
808
809 /*
810 * So far only I2C uses 16-bit read access with clockactivity with revision
811 * in two registers with stride of 4. We can detect this based on the rev
812 * register size to configure things far enough to be able to properly read
813 * the revision register.
814 */
sysc_check_quirk_16bit(struct sysc * ddata,struct resource * res)815 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
816 {
817 if (resource_size(res) == 8)
818 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
819 }
820
821 /**
822 * sysc_parse_one - parses the interconnect target module registers
823 * @ddata: device driver data
824 * @reg: register to parse
825 */
sysc_parse_one(struct sysc * ddata,enum sysc_registers reg)826 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
827 {
828 struct resource *res;
829 const char *name;
830
831 switch (reg) {
832 case SYSC_REVISION:
833 case SYSC_SYSCONFIG:
834 case SYSC_SYSSTATUS:
835 name = reg_names[reg];
836 break;
837 default:
838 return -EINVAL;
839 }
840
841 res = platform_get_resource_byname(to_platform_device(ddata->dev),
842 IORESOURCE_MEM, name);
843 if (!res) {
844 ddata->offsets[reg] = -ENODEV;
845
846 return 0;
847 }
848
849 ddata->offsets[reg] = res->start - ddata->module_pa;
850 if (reg == SYSC_REVISION)
851 sysc_check_quirk_16bit(ddata, res);
852
853 return 0;
854 }
855
sysc_parse_registers(struct sysc * ddata)856 static int sysc_parse_registers(struct sysc *ddata)
857 {
858 int i, error;
859
860 for (i = 0; i < SYSC_MAX_REGS; i++) {
861 error = sysc_parse_one(ddata, i);
862 if (error)
863 return error;
864 }
865
866 return 0;
867 }
868
869 /**
870 * sysc_check_registers - check for misconfigured register overlaps
871 * @ddata: device driver data
872 */
sysc_check_registers(struct sysc * ddata)873 static int sysc_check_registers(struct sysc *ddata)
874 {
875 int i, j, nr_regs = 0, nr_matches = 0;
876
877 for (i = 0; i < SYSC_MAX_REGS; i++) {
878 if (ddata->offsets[i] < 0)
879 continue;
880
881 if (ddata->offsets[i] > (ddata->module_size - 4)) {
882 dev_err(ddata->dev, "register outside module range");
883
884 return -EINVAL;
885 }
886
887 for (j = 0; j < SYSC_MAX_REGS; j++) {
888 if (ddata->offsets[j] < 0)
889 continue;
890
891 if (ddata->offsets[i] == ddata->offsets[j])
892 nr_matches++;
893 }
894 nr_regs++;
895 }
896
897 if (nr_matches > nr_regs) {
898 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
899 nr_regs, nr_matches);
900
901 return -EINVAL;
902 }
903
904 return 0;
905 }
906
907 /**
908 * sysc_ioremap - ioremap register space for the interconnect target module
909 * @ddata: device driver data
910 *
911 * Note that the interconnect target module registers can be anywhere
912 * within the interconnect target module range. For example, SGX has
913 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
914 * has them at offset 0x1200 in the CPSW_WR child. Usually the
915 * the interconnect target module registers are at the beginning of
916 * the module range though.
917 */
sysc_ioremap(struct sysc * ddata)918 static int sysc_ioremap(struct sysc *ddata)
919 {
920 int size;
921
922 if (ddata->offsets[SYSC_REVISION] < 0 &&
923 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
924 ddata->offsets[SYSC_SYSSTATUS] < 0) {
925 size = ddata->module_size;
926 } else {
927 size = max3(ddata->offsets[SYSC_REVISION],
928 ddata->offsets[SYSC_SYSCONFIG],
929 ddata->offsets[SYSC_SYSSTATUS]);
930
931 if (size < SZ_1K)
932 size = SZ_1K;
933
934 if ((size + sizeof(u32)) > ddata->module_size)
935 size = ddata->module_size;
936 }
937
938 ddata->module_va = devm_ioremap(ddata->dev,
939 ddata->module_pa,
940 size + sizeof(u32));
941 if (!ddata->module_va)
942 return -EIO;
943
944 return 0;
945 }
946
947 /**
948 * sysc_map_and_check_registers - ioremap and check device registers
949 * @ddata: device driver data
950 */
sysc_map_and_check_registers(struct sysc * ddata)951 static int sysc_map_and_check_registers(struct sysc *ddata)
952 {
953 struct device_node *np = ddata->dev->of_node;
954 int error;
955
956 error = sysc_parse_and_check_child_range(ddata);
957 if (error)
958 return error;
959
960 error = sysc_defer_non_critical(ddata);
961 if (error)
962 return error;
963
964 sysc_check_children(ddata);
965
966 if (!of_get_property(np, "reg", NULL))
967 return 0;
968
969 error = sysc_parse_registers(ddata);
970 if (error)
971 return error;
972
973 error = sysc_ioremap(ddata);
974 if (error)
975 return error;
976
977 error = sysc_check_registers(ddata);
978 if (error)
979 return error;
980
981 return 0;
982 }
983
984 /**
985 * sysc_show_rev - read and show interconnect target module revision
986 * @bufp: buffer to print the information to
987 * @ddata: device driver data
988 */
sysc_show_rev(char * bufp,struct sysc * ddata)989 static int sysc_show_rev(char *bufp, struct sysc *ddata)
990 {
991 int len;
992
993 if (ddata->offsets[SYSC_REVISION] < 0)
994 return sprintf(bufp, ":NA");
995
996 len = sprintf(bufp, ":%08x", ddata->revision);
997
998 return len;
999 }
1000
sysc_show_reg(struct sysc * ddata,char * bufp,enum sysc_registers reg)1001 static int sysc_show_reg(struct sysc *ddata,
1002 char *bufp, enum sysc_registers reg)
1003 {
1004 if (ddata->offsets[reg] < 0)
1005 return sprintf(bufp, ":NA");
1006
1007 return sprintf(bufp, ":%x", ddata->offsets[reg]);
1008 }
1009
sysc_show_name(char * bufp,struct sysc * ddata)1010 static int sysc_show_name(char *bufp, struct sysc *ddata)
1011 {
1012 if (!ddata->name)
1013 return 0;
1014
1015 return sprintf(bufp, ":%s", ddata->name);
1016 }
1017
1018 /**
1019 * sysc_show_registers - show information about interconnect target module
1020 * @ddata: device driver data
1021 */
sysc_show_registers(struct sysc * ddata)1022 static void sysc_show_registers(struct sysc *ddata)
1023 {
1024 char buf[128];
1025 char *bufp = buf;
1026 int i;
1027
1028 for (i = 0; i < SYSC_MAX_REGS; i++)
1029 bufp += sysc_show_reg(ddata, bufp, i);
1030
1031 bufp += sysc_show_rev(bufp, ddata);
1032 bufp += sysc_show_name(bufp, ddata);
1033
1034 dev_dbg(ddata->dev, "%llx:%x%s\n",
1035 ddata->module_pa, ddata->module_size,
1036 buf);
1037 }
1038
1039 /**
1040 * sysc_write_sysconfig - handle sysconfig quirks for register write
1041 * @ddata: device driver data
1042 * @value: register value
1043 */
sysc_write_sysconfig(struct sysc * ddata,u32 value)1044 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
1045 {
1046 if (ddata->module_unlock_quirk)
1047 ddata->module_unlock_quirk(ddata);
1048
1049 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1050
1051 if (ddata->module_lock_quirk)
1052 ddata->module_lock_quirk(ddata);
1053 }
1054
1055 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1056 #define SYSC_CLOCACT_ICK 2
1057
1058 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
sysc_enable_module(struct device * dev)1059 static int sysc_enable_module(struct device *dev)
1060 {
1061 struct sysc *ddata;
1062 const struct sysc_regbits *regbits;
1063 u32 reg, idlemodes, best_mode;
1064 int error;
1065
1066 ddata = dev_get_drvdata(dev);
1067
1068 /*
1069 * Some modules like DSS reset automatically on idle. Enable optional
1070 * reset clocks and wait for OCP softreset to complete.
1071 */
1072 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1073 error = sysc_enable_opt_clocks(ddata);
1074 if (error) {
1075 dev_err(ddata->dev,
1076 "Optional clocks failed for enable: %i\n",
1077 error);
1078 return error;
1079 }
1080 }
1081 /*
1082 * Some modules like i2c and hdq1w have unusable reset status unless
1083 * the module reset quirk is enabled. Skip status check on enable.
1084 */
1085 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1086 error = sysc_wait_softreset(ddata);
1087 if (error)
1088 dev_warn(ddata->dev, "OCP softreset timed out\n");
1089 }
1090 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1091 sysc_disable_opt_clocks(ddata);
1092
1093 /*
1094 * Some subsystem private interconnects, like DSS top level module,
1095 * need only the automatic OCP softreset handling with no sysconfig
1096 * register bits to configure.
1097 */
1098 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1099 return 0;
1100
1101 regbits = ddata->cap->regbits;
1102 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1103
1104 /*
1105 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1106 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1107 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1108 */
1109 if (regbits->clkact_shift >= 0 &&
1110 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1111 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1112
1113 /* Set SIDLE mode */
1114 idlemodes = ddata->cfg.sidlemodes;
1115 if (!idlemodes || regbits->sidle_shift < 0)
1116 goto set_midle;
1117
1118 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1119 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1120 best_mode = SYSC_IDLE_NO;
1121
1122 /* Clear WAKEUP */
1123 if (regbits->enwkup_shift >= 0 &&
1124 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1125 reg &= ~BIT(regbits->enwkup_shift);
1126 } else {
1127 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1128 if (best_mode > SYSC_IDLE_MASK) {
1129 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1130 return -EINVAL;
1131 }
1132
1133 /* Set WAKEUP */
1134 if (regbits->enwkup_shift >= 0 &&
1135 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1136 reg |= BIT(regbits->enwkup_shift);
1137 }
1138
1139 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1140 reg |= best_mode << regbits->sidle_shift;
1141 sysc_write_sysconfig(ddata, reg);
1142
1143 set_midle:
1144 /* Set MIDLE mode */
1145 idlemodes = ddata->cfg.midlemodes;
1146 if (!idlemodes || regbits->midle_shift < 0)
1147 goto set_autoidle;
1148
1149 best_mode = fls(ddata->cfg.midlemodes) - 1;
1150 if (best_mode > SYSC_IDLE_MASK) {
1151 dev_err(dev, "%s: invalid midlemode\n", __func__);
1152 return -EINVAL;
1153 }
1154
1155 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1156 best_mode = SYSC_IDLE_NO;
1157
1158 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1159 reg |= best_mode << regbits->midle_shift;
1160 sysc_write_sysconfig(ddata, reg);
1161
1162 set_autoidle:
1163 /* Autoidle bit must enabled separately if available */
1164 if (regbits->autoidle_shift >= 0 &&
1165 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1166 reg |= 1 << regbits->autoidle_shift;
1167 sysc_write_sysconfig(ddata, reg);
1168 }
1169
1170 /* Flush posted write */
1171 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1172
1173 if (ddata->module_enable_quirk)
1174 ddata->module_enable_quirk(ddata);
1175
1176 return 0;
1177 }
1178
sysc_best_idle_mode(u32 idlemodes,u32 * best_mode)1179 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1180 {
1181 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1182 *best_mode = SYSC_IDLE_SMART_WKUP;
1183 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1184 *best_mode = SYSC_IDLE_SMART;
1185 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1186 *best_mode = SYSC_IDLE_FORCE;
1187 else
1188 return -EINVAL;
1189
1190 return 0;
1191 }
1192
1193 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
sysc_disable_module(struct device * dev)1194 static int sysc_disable_module(struct device *dev)
1195 {
1196 struct sysc *ddata;
1197 const struct sysc_regbits *regbits;
1198 u32 reg, idlemodes, best_mode;
1199 int ret;
1200
1201 ddata = dev_get_drvdata(dev);
1202 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1203 return 0;
1204
1205 if (ddata->module_disable_quirk)
1206 ddata->module_disable_quirk(ddata);
1207
1208 regbits = ddata->cap->regbits;
1209 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1210
1211 /* Set MIDLE mode */
1212 idlemodes = ddata->cfg.midlemodes;
1213 if (!idlemodes || regbits->midle_shift < 0)
1214 goto set_sidle;
1215
1216 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1217 if (ret) {
1218 dev_err(dev, "%s: invalid midlemode\n", __func__);
1219 return ret;
1220 }
1221
1222 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1223 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1224 best_mode = SYSC_IDLE_FORCE;
1225
1226 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1227 reg |= best_mode << regbits->midle_shift;
1228 sysc_write_sysconfig(ddata, reg);
1229
1230 set_sidle:
1231 /* Set SIDLE mode */
1232 idlemodes = ddata->cfg.sidlemodes;
1233 if (!idlemodes || regbits->sidle_shift < 0)
1234 return 0;
1235
1236 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1237 best_mode = SYSC_IDLE_FORCE;
1238 } else {
1239 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1240 if (ret) {
1241 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1242 return ret;
1243 }
1244 }
1245
1246 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT) {
1247 /* Set WAKEUP */
1248 if (regbits->enwkup_shift >= 0 &&
1249 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1250 reg |= BIT(regbits->enwkup_shift);
1251 }
1252
1253 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1254 reg |= best_mode << regbits->sidle_shift;
1255 if (regbits->autoidle_shift >= 0 &&
1256 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1257 reg |= 1 << regbits->autoidle_shift;
1258 sysc_write_sysconfig(ddata, reg);
1259
1260 /* Flush posted write */
1261 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1262
1263 return 0;
1264 }
1265
sysc_runtime_suspend_legacy(struct device * dev,struct sysc * ddata)1266 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1267 struct sysc *ddata)
1268 {
1269 struct ti_sysc_platform_data *pdata;
1270 int error;
1271
1272 pdata = dev_get_platdata(ddata->dev);
1273 if (!pdata)
1274 return 0;
1275
1276 if (!pdata->idle_module)
1277 return -ENODEV;
1278
1279 error = pdata->idle_module(dev, &ddata->cookie);
1280 if (error)
1281 dev_err(dev, "%s: could not idle: %i\n",
1282 __func__, error);
1283
1284 reset_control_assert(ddata->rsts);
1285
1286 return 0;
1287 }
1288
sysc_runtime_resume_legacy(struct device * dev,struct sysc * ddata)1289 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1290 struct sysc *ddata)
1291 {
1292 struct ti_sysc_platform_data *pdata;
1293 int error;
1294
1295 pdata = dev_get_platdata(ddata->dev);
1296 if (!pdata)
1297 return 0;
1298
1299 if (!pdata->enable_module)
1300 return -ENODEV;
1301
1302 error = pdata->enable_module(dev, &ddata->cookie);
1303 if (error)
1304 dev_err(dev, "%s: could not enable: %i\n",
1305 __func__, error);
1306
1307 reset_control_deassert(ddata->rsts);
1308
1309 return 0;
1310 }
1311
sysc_runtime_suspend(struct device * dev)1312 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1313 {
1314 struct sysc *ddata;
1315 int error = 0;
1316
1317 ddata = dev_get_drvdata(dev);
1318
1319 if (!ddata->enabled)
1320 return 0;
1321
1322 sysc_clkdm_deny_idle(ddata);
1323
1324 if (ddata->legacy_mode) {
1325 error = sysc_runtime_suspend_legacy(dev, ddata);
1326 if (error)
1327 goto err_allow_idle;
1328 } else {
1329 error = sysc_disable_module(dev);
1330 if (error)
1331 goto err_allow_idle;
1332 }
1333
1334 sysc_disable_main_clocks(ddata);
1335
1336 if (sysc_opt_clks_needed(ddata))
1337 sysc_disable_opt_clocks(ddata);
1338
1339 ddata->enabled = false;
1340
1341 err_allow_idle:
1342 sysc_clkdm_allow_idle(ddata);
1343
1344 reset_control_assert(ddata->rsts);
1345
1346 return error;
1347 }
1348
sysc_runtime_resume(struct device * dev)1349 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1350 {
1351 struct sysc *ddata;
1352 int error = 0;
1353
1354 ddata = dev_get_drvdata(dev);
1355
1356 if (ddata->enabled)
1357 return 0;
1358
1359
1360 sysc_clkdm_deny_idle(ddata);
1361
1362 if (sysc_opt_clks_needed(ddata)) {
1363 error = sysc_enable_opt_clocks(ddata);
1364 if (error)
1365 goto err_allow_idle;
1366 }
1367
1368 error = sysc_enable_main_clocks(ddata);
1369 if (error)
1370 goto err_opt_clocks;
1371
1372 reset_control_deassert(ddata->rsts);
1373
1374 if (ddata->legacy_mode) {
1375 error = sysc_runtime_resume_legacy(dev, ddata);
1376 if (error)
1377 goto err_main_clocks;
1378 } else {
1379 error = sysc_enable_module(dev);
1380 if (error)
1381 goto err_main_clocks;
1382 }
1383
1384 ddata->enabled = true;
1385
1386 sysc_clkdm_allow_idle(ddata);
1387
1388 return 0;
1389
1390 err_main_clocks:
1391 sysc_disable_main_clocks(ddata);
1392 err_opt_clocks:
1393 if (sysc_opt_clks_needed(ddata))
1394 sysc_disable_opt_clocks(ddata);
1395 err_allow_idle:
1396 sysc_clkdm_allow_idle(ddata);
1397
1398 return error;
1399 }
1400
sysc_reinit_module(struct sysc * ddata,bool leave_enabled)1401 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1402 {
1403 struct device *dev = ddata->dev;
1404 int error;
1405
1406 /* Disable target module if it is enabled */
1407 if (ddata->enabled) {
1408 error = sysc_runtime_suspend(dev);
1409 if (error)
1410 dev_warn(dev, "reinit suspend failed: %i\n", error);
1411 }
1412
1413 /* Enable target module */
1414 error = sysc_runtime_resume(dev);
1415 if (error)
1416 dev_warn(dev, "reinit resume failed: %i\n", error);
1417
1418 if (leave_enabled)
1419 return error;
1420
1421 /* Disable target module if no leave_enabled was set */
1422 error = sysc_runtime_suspend(dev);
1423 if (error)
1424 dev_warn(dev, "reinit suspend failed: %i\n", error);
1425
1426 return error;
1427 }
1428
sysc_noirq_suspend(struct device * dev)1429 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1430 {
1431 struct sysc *ddata;
1432
1433 ddata = dev_get_drvdata(dev);
1434
1435 if (ddata->cfg.quirks &
1436 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1437 return 0;
1438
1439 if (!ddata->enabled)
1440 return 0;
1441
1442 ddata->needs_resume = 1;
1443
1444 return sysc_runtime_suspend(dev);
1445 }
1446
sysc_noirq_resume(struct device * dev)1447 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1448 {
1449 struct sysc *ddata;
1450 int error = 0;
1451
1452 ddata = dev_get_drvdata(dev);
1453
1454 if (ddata->cfg.quirks &
1455 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1456 return 0;
1457
1458 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1459 error = sysc_reinit_module(ddata, ddata->needs_resume);
1460 if (error)
1461 dev_warn(dev, "noirq_resume failed: %i\n", error);
1462 } else if (ddata->needs_resume) {
1463 error = sysc_runtime_resume(dev);
1464 if (error)
1465 dev_warn(dev, "noirq_resume failed: %i\n", error);
1466 }
1467
1468 ddata->needs_resume = 0;
1469
1470 return error;
1471 }
1472
1473 static const struct dev_pm_ops sysc_pm_ops = {
1474 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1475 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1476 sysc_runtime_resume,
1477 NULL)
1478 };
1479
1480 /* Module revision register based quirks */
1481 struct sysc_revision_quirk {
1482 const char *name;
1483 u32 base;
1484 int rev_offset;
1485 int sysc_offset;
1486 int syss_offset;
1487 u32 revision;
1488 u32 revision_mask;
1489 u32 quirks;
1490 };
1491
1492 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1493 optrev_val, optrevmask, optquirkmask) \
1494 { \
1495 .name = (optname), \
1496 .base = (optbase), \
1497 .rev_offset = (optrev), \
1498 .sysc_offset = (optsysc), \
1499 .syss_offset = (optsyss), \
1500 .revision = (optrev_val), \
1501 .revision_mask = (optrevmask), \
1502 .quirks = (optquirkmask), \
1503 }
1504
1505 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1506 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1507 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1508 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1509 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1510 SYSC_QUIRK_LEGACY_IDLE),
1511 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1512 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1513 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1514 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1515 /* Uarts on omap4 and later */
1516 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1517 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1518 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1519 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1520 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff,
1521 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1522
1523 /* Quirks that need to be set based on the module address */
1524 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1525 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1526 SYSC_QUIRK_SWSUP_SIDLE),
1527
1528 /* Quirks that need to be set based on detected module */
1529 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1530 SYSC_MODULE_QUIRK_AESS),
1531 /* Errata i893 handling for dra7 dcan1 and 2 */
1532 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1533 SYSC_QUIRK_CLKDM_NOAUTO),
1534 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1535 SYSC_QUIRK_CLKDM_NOAUTO),
1536 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1537 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1538 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1539 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1540 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1541 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1542 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1543 SYSC_QUIRK_CLKDM_NOAUTO),
1544 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1545 SYSC_QUIRK_CLKDM_NOAUTO),
1546 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1547 SYSC_QUIRK_GPMC_DEBUG),
1548 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1549 SYSC_QUIRK_OPT_CLKS_NEEDED),
1550 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1551 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1552 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1553 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1554 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1555 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1556 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1557 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1558 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1559 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1560 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1561 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1562 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1563 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1564 SYSC_MODULE_QUIRK_SGX),
1565 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1566 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1567 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1568 SYSC_QUIRK_SWSUP_SIDLE),
1569 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1570 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1571 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1572 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1573 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1574 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1575 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1576 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1577 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1578 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1579 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1580 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1581 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1582 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1583 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1584 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1585 SYSC_QUIRK_REINIT_ON_CTX_LOST),
1586 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1587 SYSC_MODULE_QUIRK_WDT),
1588 /* PRUSS on am3, am4 and am5 */
1589 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1590 SYSC_MODULE_QUIRK_PRUSS),
1591 /* Watchdog on am3 and am4 */
1592 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1593 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1594
1595 #ifdef DEBUG
1596 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1597 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1598 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1599 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1600 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1601 0xffff00f0, 0),
1602 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1603 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1604 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1605 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1606 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1607 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1608 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1609 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1610 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1611 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1612 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1613 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1614 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1615 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1616 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1617 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1618 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1619 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1620 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1621 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1622 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1623 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1624 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1625 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1626 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1627 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1628 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1629 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1630 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1631 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1632 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1633 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1634 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1635 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1636 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1637 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1638 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1639 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1640 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1641 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1642 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1643 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1644 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1645 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1646 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1647 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1648 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1649 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1650 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1651 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1652 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1653 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
1654 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1655 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1656 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1657 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1658 /* Some timers on omap4 and later */
1659 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1660 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1661 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1662 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1663 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1664 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1665 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1666 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1667 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1668 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1669 #endif
1670 };
1671
1672 /*
1673 * Early quirks based on module base and register offsets only that are
1674 * needed before the module revision can be read
1675 */
sysc_init_early_quirks(struct sysc * ddata)1676 static void sysc_init_early_quirks(struct sysc *ddata)
1677 {
1678 const struct sysc_revision_quirk *q;
1679 int i;
1680
1681 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1682 q = &sysc_revision_quirks[i];
1683
1684 if (!q->base)
1685 continue;
1686
1687 if (q->base != ddata->module_pa)
1688 continue;
1689
1690 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1691 continue;
1692
1693 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1694 continue;
1695
1696 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1697 continue;
1698
1699 ddata->name = q->name;
1700 ddata->cfg.quirks |= q->quirks;
1701 }
1702 }
1703
1704 /* Quirks that also consider the revision register value */
sysc_init_revision_quirks(struct sysc * ddata)1705 static void sysc_init_revision_quirks(struct sysc *ddata)
1706 {
1707 const struct sysc_revision_quirk *q;
1708 int i;
1709
1710 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1711 q = &sysc_revision_quirks[i];
1712
1713 if (q->base && q->base != ddata->module_pa)
1714 continue;
1715
1716 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1717 continue;
1718
1719 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1720 continue;
1721
1722 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1723 continue;
1724
1725 if (q->revision == ddata->revision ||
1726 (q->revision & q->revision_mask) ==
1727 (ddata->revision & q->revision_mask)) {
1728 ddata->name = q->name;
1729 ddata->cfg.quirks |= q->quirks;
1730 }
1731 }
1732 }
1733
1734 /*
1735 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1736 * enabled DSS interrupts. Eventually we may be able to do this on
1737 * dispc init rather than top-level DSS init.
1738 */
sysc_quirk_dispc(struct sysc * ddata,int dispc_offset,bool disable)1739 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1740 bool disable)
1741 {
1742 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1743 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1744 int manager_count;
1745 bool framedonetv_irq = true;
1746 u32 val, irq_mask = 0;
1747
1748 switch (sysc_soc->soc) {
1749 case SOC_2420 ... SOC_3630:
1750 manager_count = 2;
1751 framedonetv_irq = false;
1752 break;
1753 case SOC_4430 ... SOC_4470:
1754 manager_count = 3;
1755 break;
1756 case SOC_5430:
1757 case SOC_DRA7:
1758 manager_count = 4;
1759 break;
1760 case SOC_AM4:
1761 manager_count = 1;
1762 framedonetv_irq = false;
1763 break;
1764 case SOC_UNKNOWN:
1765 default:
1766 return 0;
1767 }
1768
1769 /* Remap the whole module range to be able to reset dispc outputs */
1770 devm_iounmap(ddata->dev, ddata->module_va);
1771 ddata->module_va = devm_ioremap(ddata->dev,
1772 ddata->module_pa,
1773 ddata->module_size);
1774 if (!ddata->module_va)
1775 return -EIO;
1776
1777 /* DISP_CONTROL, shut down lcd and digit on disable if enabled */
1778 val = sysc_read(ddata, dispc_offset + 0x40);
1779 lcd_en = val & lcd_en_mask;
1780 digit_en = val & digit_en_mask;
1781 if (lcd_en)
1782 irq_mask |= BIT(0); /* FRAMEDONE */
1783 if (digit_en) {
1784 if (framedonetv_irq)
1785 irq_mask |= BIT(24); /* FRAMEDONETV */
1786 else
1787 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1788 }
1789 if (disable && (lcd_en || digit_en))
1790 sysc_write(ddata, dispc_offset + 0x40,
1791 val & ~(lcd_en_mask | digit_en_mask));
1792
1793 if (manager_count <= 2)
1794 return irq_mask;
1795
1796 /* DISPC_CONTROL2 */
1797 val = sysc_read(ddata, dispc_offset + 0x238);
1798 lcd2_en = val & lcd_en_mask;
1799 if (lcd2_en)
1800 irq_mask |= BIT(22); /* FRAMEDONE2 */
1801 if (disable && lcd2_en)
1802 sysc_write(ddata, dispc_offset + 0x238,
1803 val & ~lcd_en_mask);
1804
1805 if (manager_count <= 3)
1806 return irq_mask;
1807
1808 /* DISPC_CONTROL3 */
1809 val = sysc_read(ddata, dispc_offset + 0x848);
1810 lcd3_en = val & lcd_en_mask;
1811 if (lcd3_en)
1812 irq_mask |= BIT(30); /* FRAMEDONE3 */
1813 if (disable && lcd3_en)
1814 sysc_write(ddata, dispc_offset + 0x848,
1815 val & ~lcd_en_mask);
1816
1817 return irq_mask;
1818 }
1819
1820 /* DSS needs child outputs disabled and SDI registers cleared for reset */
sysc_pre_reset_quirk_dss(struct sysc * ddata)1821 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1822 {
1823 const int dispc_offset = 0x1000;
1824 int error;
1825 u32 irq_mask, val;
1826
1827 /* Get enabled outputs */
1828 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1829 if (!irq_mask)
1830 return;
1831
1832 /* Clear IRQSTATUS */
1833 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1834
1835 /* Disable outputs */
1836 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1837
1838 /* Poll IRQSTATUS */
1839 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1840 val, val != irq_mask, 100, 50);
1841 if (error)
1842 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1843 __func__, val, irq_mask);
1844
1845 if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) {
1846 /* Clear DSS_SDI_CONTROL */
1847 sysc_write(ddata, 0x44, 0);
1848
1849 /* Clear DSS_PLL_CONTROL */
1850 sysc_write(ddata, 0x48, 0);
1851 }
1852
1853 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1854 sysc_write(ddata, 0x40, 0);
1855 }
1856
1857 /* 1-wire needs module's internal clocks enabled for reset */
sysc_pre_reset_quirk_hdq1w(struct sysc * ddata)1858 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1859 {
1860 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1861 u16 val;
1862
1863 val = sysc_read(ddata, offset);
1864 val |= BIT(5);
1865 sysc_write(ddata, offset, val);
1866 }
1867
1868 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
sysc_module_enable_quirk_aess(struct sysc * ddata)1869 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1870 {
1871 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1872
1873 sysc_write(ddata, offset, 1);
1874 }
1875
1876 /* I2C needs to be disabled for reset */
sysc_clk_quirk_i2c(struct sysc * ddata,bool enable)1877 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1878 {
1879 int offset;
1880 u16 val;
1881
1882 /* I2C_CON, omap2/3 is different from omap4 and later */
1883 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1884 offset = 0x24;
1885 else
1886 offset = 0xa4;
1887
1888 /* I2C_EN */
1889 val = sysc_read(ddata, offset);
1890 if (enable)
1891 val |= BIT(15);
1892 else
1893 val &= ~BIT(15);
1894 sysc_write(ddata, offset, val);
1895 }
1896
sysc_pre_reset_quirk_i2c(struct sysc * ddata)1897 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1898 {
1899 sysc_clk_quirk_i2c(ddata, false);
1900 }
1901
sysc_post_reset_quirk_i2c(struct sysc * ddata)1902 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1903 {
1904 sysc_clk_quirk_i2c(ddata, true);
1905 }
1906
1907 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
sysc_quirk_rtc(struct sysc * ddata,bool lock)1908 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1909 {
1910 u32 val, kick0_val = 0, kick1_val = 0;
1911 unsigned long flags;
1912 int error;
1913
1914 if (!lock) {
1915 kick0_val = 0x83e70b13;
1916 kick1_val = 0x95a4f1e0;
1917 }
1918
1919 local_irq_save(flags);
1920 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1921 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1922 !(val & BIT(0)), 100, 50);
1923 if (error)
1924 dev_warn(ddata->dev, "rtc busy timeout\n");
1925 /* Now we have ~15 microseconds to read/write various registers */
1926 sysc_write(ddata, 0x6c, kick0_val);
1927 sysc_write(ddata, 0x70, kick1_val);
1928 local_irq_restore(flags);
1929 }
1930
sysc_module_unlock_quirk_rtc(struct sysc * ddata)1931 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1932 {
1933 sysc_quirk_rtc(ddata, false);
1934 }
1935
sysc_module_lock_quirk_rtc(struct sysc * ddata)1936 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1937 {
1938 sysc_quirk_rtc(ddata, true);
1939 }
1940
1941 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
sysc_module_enable_quirk_sgx(struct sysc * ddata)1942 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1943 {
1944 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1945 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1946
1947 sysc_write(ddata, offset, val);
1948 }
1949
1950 /* Watchdog timer needs a disable sequence after reset */
sysc_reset_done_quirk_wdt(struct sysc * ddata)1951 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1952 {
1953 int wps, spr, error;
1954 u32 val;
1955
1956 wps = 0x34;
1957 spr = 0x48;
1958
1959 sysc_write(ddata, spr, 0xaaaa);
1960 error = readl_poll_timeout(ddata->module_va + wps, val,
1961 !(val & 0x10), 100,
1962 MAX_MODULE_SOFTRESET_WAIT);
1963 if (error)
1964 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1965
1966 sysc_write(ddata, spr, 0x5555);
1967 error = readl_poll_timeout(ddata->module_va + wps, val,
1968 !(val & 0x10), 100,
1969 MAX_MODULE_SOFTRESET_WAIT);
1970 if (error)
1971 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1972 }
1973
1974 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
sysc_module_disable_quirk_pruss(struct sysc * ddata)1975 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1976 {
1977 u32 reg;
1978
1979 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1980 reg |= SYSC_PRUSS_STANDBY_INIT;
1981 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1982 }
1983
sysc_init_module_quirks(struct sysc * ddata)1984 static void sysc_init_module_quirks(struct sysc *ddata)
1985 {
1986 if (ddata->legacy_mode || !ddata->name)
1987 return;
1988
1989 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1990 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1991
1992 return;
1993 }
1994
1995 #ifdef CONFIG_OMAP_GPMC_DEBUG
1996 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
1997 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
1998
1999 return;
2000 }
2001 #endif
2002
2003 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
2004 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
2005 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
2006
2007 return;
2008 }
2009
2010 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
2011 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
2012
2013 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
2014 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
2015
2016 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
2017 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
2018 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
2019
2020 return;
2021 }
2022
2023 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
2024 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2025
2026 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
2027 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
2028 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2029 }
2030
2031 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
2032 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
2033 }
2034
sysc_clockdomain_init(struct sysc * ddata)2035 static int sysc_clockdomain_init(struct sysc *ddata)
2036 {
2037 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2038 struct clk *fck = NULL, *ick = NULL;
2039 int error;
2040
2041 if (!pdata || !pdata->init_clockdomain)
2042 return 0;
2043
2044 switch (ddata->nr_clocks) {
2045 case 2:
2046 ick = ddata->clocks[SYSC_ICK];
2047 fallthrough;
2048 case 1:
2049 fck = ddata->clocks[SYSC_FCK];
2050 break;
2051 case 0:
2052 return 0;
2053 }
2054
2055 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2056 if (!error || error == -ENODEV)
2057 return 0;
2058
2059 return error;
2060 }
2061
2062 /*
2063 * Note that pdata->init_module() typically does a reset first. After
2064 * pdata->init_module() is done, PM runtime can be used for the interconnect
2065 * target module.
2066 */
sysc_legacy_init(struct sysc * ddata)2067 static int sysc_legacy_init(struct sysc *ddata)
2068 {
2069 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2070 int error;
2071
2072 if (!pdata || !pdata->init_module)
2073 return 0;
2074
2075 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2076 if (error == -EEXIST)
2077 error = 0;
2078
2079 return error;
2080 }
2081
2082 /*
2083 * Note that the caller must ensure the interconnect target module is enabled
2084 * before calling reset. Otherwise reset will not complete.
2085 */
sysc_reset(struct sysc * ddata)2086 static int sysc_reset(struct sysc *ddata)
2087 {
2088 int sysc_offset, sysc_val, error;
2089 u32 sysc_mask;
2090
2091 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2092
2093 if (ddata->legacy_mode ||
2094 ddata->cap->regbits->srst_shift < 0 ||
2095 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2096 return 0;
2097
2098 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2099
2100 if (ddata->pre_reset_quirk)
2101 ddata->pre_reset_quirk(ddata);
2102
2103 if (sysc_offset >= 0) {
2104 sysc_val = sysc_read_sysconfig(ddata);
2105 sysc_val |= sysc_mask;
2106 sysc_write(ddata, sysc_offset, sysc_val);
2107
2108 /*
2109 * Some devices need a delay before reading registers
2110 * after reset. Presumably a srst_udelay is not needed
2111 * for devices that use a rstctrl register reset.
2112 */
2113 if (ddata->cfg.srst_udelay)
2114 fsleep(ddata->cfg.srst_udelay);
2115
2116 /*
2117 * Flush posted write. For devices needing srst_udelay
2118 * this should trigger an interconnect error if the
2119 * srst_udelay value is needed but not configured.
2120 */
2121 sysc_val = sysc_read_sysconfig(ddata);
2122 }
2123
2124 if (ddata->post_reset_quirk)
2125 ddata->post_reset_quirk(ddata);
2126
2127 error = sysc_wait_softreset(ddata);
2128 if (error)
2129 dev_warn(ddata->dev, "OCP softreset timed out\n");
2130
2131 if (ddata->reset_done_quirk)
2132 ddata->reset_done_quirk(ddata);
2133
2134 return error;
2135 }
2136
2137 /*
2138 * At this point the module is configured enough to read the revision but
2139 * module may not be completely configured yet to use PM runtime. Enable
2140 * all clocks directly during init to configure the quirks needed for PM
2141 * runtime based on the revision register.
2142 */
sysc_init_module(struct sysc * ddata)2143 static int sysc_init_module(struct sysc *ddata)
2144 {
2145 bool rstctrl_deasserted = false;
2146 int error = 0;
2147
2148 error = sysc_clockdomain_init(ddata);
2149 if (error)
2150 return error;
2151
2152 sysc_clkdm_deny_idle(ddata);
2153
2154 /*
2155 * Always enable clocks. The bootloader may or may not have enabled
2156 * the related clocks.
2157 */
2158 error = sysc_enable_opt_clocks(ddata);
2159 if (error)
2160 return error;
2161
2162 error = sysc_enable_main_clocks(ddata);
2163 if (error)
2164 goto err_opt_clocks;
2165
2166 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2167 error = reset_control_deassert(ddata->rsts);
2168 if (error)
2169 goto err_main_clocks;
2170 rstctrl_deasserted = true;
2171 }
2172
2173 ddata->revision = sysc_read_revision(ddata);
2174 sysc_init_revision_quirks(ddata);
2175 sysc_init_module_quirks(ddata);
2176
2177 if (ddata->legacy_mode) {
2178 error = sysc_legacy_init(ddata);
2179 if (error)
2180 goto err_main_clocks;
2181 }
2182
2183 if (!ddata->legacy_mode) {
2184 error = sysc_enable_module(ddata->dev);
2185 if (error)
2186 goto err_main_clocks;
2187 }
2188
2189 error = sysc_reset(ddata);
2190 if (error)
2191 dev_err(ddata->dev, "Reset failed with %d\n", error);
2192
2193 if (error && !ddata->legacy_mode)
2194 sysc_disable_module(ddata->dev);
2195
2196 err_main_clocks:
2197 if (error)
2198 sysc_disable_main_clocks(ddata);
2199 err_opt_clocks:
2200 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2201 if (error) {
2202 sysc_disable_opt_clocks(ddata);
2203 sysc_clkdm_allow_idle(ddata);
2204 }
2205
2206 if (error && rstctrl_deasserted &&
2207 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2208 reset_control_assert(ddata->rsts);
2209
2210 return error;
2211 }
2212
sysc_init_sysc_mask(struct sysc * ddata)2213 static int sysc_init_sysc_mask(struct sysc *ddata)
2214 {
2215 struct device_node *np = ddata->dev->of_node;
2216 int error;
2217 u32 val;
2218
2219 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2220 if (error)
2221 return 0;
2222
2223 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2224
2225 return 0;
2226 }
2227
sysc_init_idlemode(struct sysc * ddata,u8 * idlemodes,const char * name)2228 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2229 const char *name)
2230 {
2231 struct device_node *np = ddata->dev->of_node;
2232 struct property *prop;
2233 const __be32 *p;
2234 u32 val;
2235
2236 of_property_for_each_u32(np, name, prop, p, val) {
2237 if (val >= SYSC_NR_IDLEMODES) {
2238 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2239 return -EINVAL;
2240 }
2241 *idlemodes |= (1 << val);
2242 }
2243
2244 return 0;
2245 }
2246
sysc_init_idlemodes(struct sysc * ddata)2247 static int sysc_init_idlemodes(struct sysc *ddata)
2248 {
2249 int error;
2250
2251 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2252 "ti,sysc-midle");
2253 if (error)
2254 return error;
2255
2256 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2257 "ti,sysc-sidle");
2258 if (error)
2259 return error;
2260
2261 return 0;
2262 }
2263
2264 /*
2265 * Only some devices on omap4 and later have SYSCONFIG reset done
2266 * bit. We can detect this if there is no SYSSTATUS at all, or the
2267 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2268 * have multiple bits for the child devices like OHCI and EHCI.
2269 * Depends on SYSC being parsed first.
2270 */
sysc_init_syss_mask(struct sysc * ddata)2271 static int sysc_init_syss_mask(struct sysc *ddata)
2272 {
2273 struct device_node *np = ddata->dev->of_node;
2274 int error;
2275 u32 val;
2276
2277 error = of_property_read_u32(np, "ti,syss-mask", &val);
2278 if (error) {
2279 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2280 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2281 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2282 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2283
2284 return 0;
2285 }
2286
2287 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2288 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2289
2290 ddata->cfg.syss_mask = val;
2291
2292 return 0;
2293 }
2294
2295 /*
2296 * Many child device drivers need to have fck and opt clocks available
2297 * to get the clock rate for device internal configuration etc.
2298 */
sysc_child_add_named_clock(struct sysc * ddata,struct device * child,const char * name)2299 static int sysc_child_add_named_clock(struct sysc *ddata,
2300 struct device *child,
2301 const char *name)
2302 {
2303 struct clk *clk;
2304 struct clk_lookup *l;
2305 int error = 0;
2306
2307 if (!name)
2308 return 0;
2309
2310 clk = clk_get(child, name);
2311 if (!IS_ERR(clk)) {
2312 error = -EEXIST;
2313 goto put_clk;
2314 }
2315
2316 clk = clk_get(ddata->dev, name);
2317 if (IS_ERR(clk))
2318 return -ENODEV;
2319
2320 l = clkdev_create(clk, name, dev_name(child));
2321 if (!l)
2322 error = -ENOMEM;
2323 put_clk:
2324 clk_put(clk);
2325
2326 return error;
2327 }
2328
sysc_child_add_clocks(struct sysc * ddata,struct device * child)2329 static int sysc_child_add_clocks(struct sysc *ddata,
2330 struct device *child)
2331 {
2332 int i, error;
2333
2334 for (i = 0; i < ddata->nr_clocks; i++) {
2335 error = sysc_child_add_named_clock(ddata,
2336 child,
2337 ddata->clock_roles[i]);
2338 if (error && error != -EEXIST) {
2339 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2340 ddata->clock_roles[i], error);
2341
2342 return error;
2343 }
2344 }
2345
2346 return 0;
2347 }
2348
2349 static struct device_type sysc_device_type = {
2350 };
2351
sysc_child_to_parent(struct device * dev)2352 static struct sysc *sysc_child_to_parent(struct device *dev)
2353 {
2354 struct device *parent = dev->parent;
2355
2356 if (!parent || parent->type != &sysc_device_type)
2357 return NULL;
2358
2359 return dev_get_drvdata(parent);
2360 }
2361
sysc_child_runtime_suspend(struct device * dev)2362 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2363 {
2364 struct sysc *ddata;
2365 int error;
2366
2367 ddata = sysc_child_to_parent(dev);
2368
2369 error = pm_generic_runtime_suspend(dev);
2370 if (error)
2371 return error;
2372
2373 if (!ddata->enabled)
2374 return 0;
2375
2376 return sysc_runtime_suspend(ddata->dev);
2377 }
2378
sysc_child_runtime_resume(struct device * dev)2379 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2380 {
2381 struct sysc *ddata;
2382 int error;
2383
2384 ddata = sysc_child_to_parent(dev);
2385
2386 if (!ddata->enabled) {
2387 error = sysc_runtime_resume(ddata->dev);
2388 if (error < 0)
2389 dev_err(ddata->dev,
2390 "%s error: %i\n", __func__, error);
2391 }
2392
2393 return pm_generic_runtime_resume(dev);
2394 }
2395
2396 #ifdef CONFIG_PM_SLEEP
sysc_child_suspend_noirq(struct device * dev)2397 static int sysc_child_suspend_noirq(struct device *dev)
2398 {
2399 struct sysc *ddata;
2400 int error;
2401
2402 ddata = sysc_child_to_parent(dev);
2403
2404 dev_dbg(ddata->dev, "%s %s\n", __func__,
2405 ddata->name ? ddata->name : "");
2406
2407 error = pm_generic_suspend_noirq(dev);
2408 if (error) {
2409 dev_err(dev, "%s error at %i: %i\n",
2410 __func__, __LINE__, error);
2411
2412 return error;
2413 }
2414
2415 if (!pm_runtime_status_suspended(dev)) {
2416 error = pm_generic_runtime_suspend(dev);
2417 if (error) {
2418 dev_dbg(dev, "%s busy at %i: %i\n",
2419 __func__, __LINE__, error);
2420
2421 return 0;
2422 }
2423
2424 error = sysc_runtime_suspend(ddata->dev);
2425 if (error) {
2426 dev_err(dev, "%s error at %i: %i\n",
2427 __func__, __LINE__, error);
2428
2429 return error;
2430 }
2431
2432 ddata->child_needs_resume = true;
2433 }
2434
2435 return 0;
2436 }
2437
sysc_child_resume_noirq(struct device * dev)2438 static int sysc_child_resume_noirq(struct device *dev)
2439 {
2440 struct sysc *ddata;
2441 int error;
2442
2443 ddata = sysc_child_to_parent(dev);
2444
2445 dev_dbg(ddata->dev, "%s %s\n", __func__,
2446 ddata->name ? ddata->name : "");
2447
2448 if (ddata->child_needs_resume) {
2449 ddata->child_needs_resume = false;
2450
2451 error = sysc_runtime_resume(ddata->dev);
2452 if (error)
2453 dev_err(ddata->dev,
2454 "%s runtime resume error: %i\n",
2455 __func__, error);
2456
2457 error = pm_generic_runtime_resume(dev);
2458 if (error)
2459 dev_err(ddata->dev,
2460 "%s generic runtime resume: %i\n",
2461 __func__, error);
2462 }
2463
2464 return pm_generic_resume_noirq(dev);
2465 }
2466 #endif
2467
2468 static struct dev_pm_domain sysc_child_pm_domain = {
2469 .ops = {
2470 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2471 sysc_child_runtime_resume,
2472 NULL)
2473 USE_PLATFORM_PM_SLEEP_OPS
2474 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2475 sysc_child_resume_noirq)
2476 }
2477 };
2478
2479 /* Caller needs to take list_lock if ever used outside of cpu_pm */
sysc_reinit_modules(struct sysc_soc_info * soc)2480 static void sysc_reinit_modules(struct sysc_soc_info *soc)
2481 {
2482 struct sysc_module *module;
2483 struct list_head *pos;
2484 struct sysc *ddata;
2485
2486 list_for_each(pos, &sysc_soc->restored_modules) {
2487 module = list_entry(pos, struct sysc_module, node);
2488 ddata = module->ddata;
2489 sysc_reinit_module(ddata, ddata->enabled);
2490 }
2491 }
2492
2493 /**
2494 * sysc_context_notifier - optionally reset and restore module after idle
2495 * @nb: notifier block
2496 * @cmd: unused
2497 * @v: unused
2498 *
2499 * Some interconnect target modules need to be restored, or reset and restored
2500 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2501 * OTG and GPMC target modules even if the modules are unused.
2502 */
sysc_context_notifier(struct notifier_block * nb,unsigned long cmd,void * v)2503 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2504 void *v)
2505 {
2506 struct sysc_soc_info *soc;
2507
2508 soc = container_of(nb, struct sysc_soc_info, nb);
2509
2510 switch (cmd) {
2511 case CPU_CLUSTER_PM_ENTER:
2512 break;
2513 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2514 break;
2515 case CPU_CLUSTER_PM_EXIT:
2516 sysc_reinit_modules(soc);
2517 break;
2518 }
2519
2520 return NOTIFY_OK;
2521 }
2522
2523 /**
2524 * sysc_add_restored - optionally add reset and restore quirk hanlling
2525 * @ddata: device data
2526 */
sysc_add_restored(struct sysc * ddata)2527 static void sysc_add_restored(struct sysc *ddata)
2528 {
2529 struct sysc_module *restored_module;
2530
2531 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
2532 if (!restored_module)
2533 return;
2534
2535 restored_module->ddata = ddata;
2536
2537 mutex_lock(&sysc_soc->list_lock);
2538
2539 list_add(&restored_module->node, &sysc_soc->restored_modules);
2540
2541 if (sysc_soc->nb.notifier_call)
2542 goto out_unlock;
2543
2544 sysc_soc->nb.notifier_call = sysc_context_notifier;
2545 cpu_pm_register_notifier(&sysc_soc->nb);
2546
2547 out_unlock:
2548 mutex_unlock(&sysc_soc->list_lock);
2549 }
2550
2551 /**
2552 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2553 * @ddata: device driver data
2554 * @child: child device driver
2555 *
2556 * Allow idle for child devices as done with _od_runtime_suspend().
2557 * Otherwise many child devices will not idle because of the permanent
2558 * parent usecount set in pm_runtime_irq_safe().
2559 *
2560 * Note that the long term solution is to just modify the child device
2561 * drivers to not set pm_runtime_irq_safe() and then this can be just
2562 * dropped.
2563 */
sysc_legacy_idle_quirk(struct sysc * ddata,struct device * child)2564 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2565 {
2566 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2567 dev_pm_domain_set(child, &sysc_child_pm_domain);
2568 }
2569
sysc_notifier_call(struct notifier_block * nb,unsigned long event,void * device)2570 static int sysc_notifier_call(struct notifier_block *nb,
2571 unsigned long event, void *device)
2572 {
2573 struct device *dev = device;
2574 struct sysc *ddata;
2575 int error;
2576
2577 ddata = sysc_child_to_parent(dev);
2578 if (!ddata)
2579 return NOTIFY_DONE;
2580
2581 switch (event) {
2582 case BUS_NOTIFY_ADD_DEVICE:
2583 error = sysc_child_add_clocks(ddata, dev);
2584 if (error)
2585 return error;
2586 sysc_legacy_idle_quirk(ddata, dev);
2587 break;
2588 default:
2589 break;
2590 }
2591
2592 return NOTIFY_DONE;
2593 }
2594
2595 static struct notifier_block sysc_nb = {
2596 .notifier_call = sysc_notifier_call,
2597 };
2598
2599 /* Device tree configured quirks */
2600 struct sysc_dts_quirk {
2601 const char *name;
2602 u32 mask;
2603 };
2604
2605 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2606 { .name = "ti,no-idle-on-init",
2607 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2608 { .name = "ti,no-reset-on-init",
2609 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2610 { .name = "ti,no-idle",
2611 .mask = SYSC_QUIRK_NO_IDLE, },
2612 };
2613
sysc_parse_dts_quirks(struct sysc * ddata,struct device_node * np,bool is_child)2614 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2615 bool is_child)
2616 {
2617 const struct property *prop;
2618 int i, len;
2619
2620 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2621 const char *name = sysc_dts_quirks[i].name;
2622
2623 prop = of_get_property(np, name, &len);
2624 if (!prop)
2625 continue;
2626
2627 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2628 if (is_child) {
2629 dev_warn(ddata->dev,
2630 "dts flag should be at module level for %s\n",
2631 name);
2632 }
2633 }
2634 }
2635
sysc_init_dts_quirks(struct sysc * ddata)2636 static int sysc_init_dts_quirks(struct sysc *ddata)
2637 {
2638 struct device_node *np = ddata->dev->of_node;
2639 int error;
2640 u32 val;
2641
2642 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2643
2644 sysc_parse_dts_quirks(ddata, np, false);
2645 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2646 if (!error) {
2647 if (val > 255) {
2648 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2649 val);
2650 }
2651
2652 ddata->cfg.srst_udelay = (u8)val;
2653 }
2654
2655 return 0;
2656 }
2657
sysc_unprepare(struct sysc * ddata)2658 static void sysc_unprepare(struct sysc *ddata)
2659 {
2660 int i;
2661
2662 if (!ddata->clocks)
2663 return;
2664
2665 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2666 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2667 clk_unprepare(ddata->clocks[i]);
2668 }
2669 }
2670
2671 /*
2672 * Common sysc register bits found on omap2, also known as type1
2673 */
2674 static const struct sysc_regbits sysc_regbits_omap2 = {
2675 .dmadisable_shift = -ENODEV,
2676 .midle_shift = 12,
2677 .sidle_shift = 3,
2678 .clkact_shift = 8,
2679 .emufree_shift = 5,
2680 .enwkup_shift = 2,
2681 .srst_shift = 1,
2682 .autoidle_shift = 0,
2683 };
2684
2685 static const struct sysc_capabilities sysc_omap2 = {
2686 .type = TI_SYSC_OMAP2,
2687 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2688 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2689 SYSC_OMAP2_AUTOIDLE,
2690 .regbits = &sysc_regbits_omap2,
2691 };
2692
2693 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2694 static const struct sysc_capabilities sysc_omap2_timer = {
2695 .type = TI_SYSC_OMAP2_TIMER,
2696 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2697 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2698 SYSC_OMAP2_AUTOIDLE,
2699 .regbits = &sysc_regbits_omap2,
2700 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2701 };
2702
2703 /*
2704 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2705 * with different sidle position
2706 */
2707 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2708 .dmadisable_shift = -ENODEV,
2709 .midle_shift = -ENODEV,
2710 .sidle_shift = 4,
2711 .clkact_shift = -ENODEV,
2712 .enwkup_shift = -ENODEV,
2713 .srst_shift = 1,
2714 .autoidle_shift = 0,
2715 .emufree_shift = -ENODEV,
2716 };
2717
2718 static const struct sysc_capabilities sysc_omap3_sham = {
2719 .type = TI_SYSC_OMAP3_SHAM,
2720 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2721 .regbits = &sysc_regbits_omap3_sham,
2722 };
2723
2724 /*
2725 * AES register bits found on omap3 and later, a variant of
2726 * sysc_regbits_omap2 with different sidle position
2727 */
2728 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2729 .dmadisable_shift = -ENODEV,
2730 .midle_shift = -ENODEV,
2731 .sidle_shift = 6,
2732 .clkact_shift = -ENODEV,
2733 .enwkup_shift = -ENODEV,
2734 .srst_shift = 1,
2735 .autoidle_shift = 0,
2736 .emufree_shift = -ENODEV,
2737 };
2738
2739 static const struct sysc_capabilities sysc_omap3_aes = {
2740 .type = TI_SYSC_OMAP3_AES,
2741 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2742 .regbits = &sysc_regbits_omap3_aes,
2743 };
2744
2745 /*
2746 * Common sysc register bits found on omap4, also known as type2
2747 */
2748 static const struct sysc_regbits sysc_regbits_omap4 = {
2749 .dmadisable_shift = 16,
2750 .midle_shift = 4,
2751 .sidle_shift = 2,
2752 .clkact_shift = -ENODEV,
2753 .enwkup_shift = -ENODEV,
2754 .emufree_shift = 1,
2755 .srst_shift = 0,
2756 .autoidle_shift = -ENODEV,
2757 };
2758
2759 static const struct sysc_capabilities sysc_omap4 = {
2760 .type = TI_SYSC_OMAP4,
2761 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2762 SYSC_OMAP4_SOFTRESET,
2763 .regbits = &sysc_regbits_omap4,
2764 };
2765
2766 static const struct sysc_capabilities sysc_omap4_timer = {
2767 .type = TI_SYSC_OMAP4_TIMER,
2768 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2769 SYSC_OMAP4_SOFTRESET,
2770 .regbits = &sysc_regbits_omap4,
2771 };
2772
2773 /*
2774 * Common sysc register bits found on omap4, also known as type3
2775 */
2776 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2777 .dmadisable_shift = -ENODEV,
2778 .midle_shift = 2,
2779 .sidle_shift = 0,
2780 .clkact_shift = -ENODEV,
2781 .enwkup_shift = -ENODEV,
2782 .srst_shift = -ENODEV,
2783 .emufree_shift = -ENODEV,
2784 .autoidle_shift = -ENODEV,
2785 };
2786
2787 static const struct sysc_capabilities sysc_omap4_simple = {
2788 .type = TI_SYSC_OMAP4_SIMPLE,
2789 .regbits = &sysc_regbits_omap4_simple,
2790 };
2791
2792 /*
2793 * SmartReflex sysc found on omap34xx
2794 */
2795 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2796 .dmadisable_shift = -ENODEV,
2797 .midle_shift = -ENODEV,
2798 .sidle_shift = -ENODEV,
2799 .clkact_shift = 20,
2800 .enwkup_shift = -ENODEV,
2801 .srst_shift = -ENODEV,
2802 .emufree_shift = -ENODEV,
2803 .autoidle_shift = -ENODEV,
2804 };
2805
2806 static const struct sysc_capabilities sysc_34xx_sr = {
2807 .type = TI_SYSC_OMAP34XX_SR,
2808 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2809 .regbits = &sysc_regbits_omap34xx_sr,
2810 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2811 SYSC_QUIRK_LEGACY_IDLE,
2812 };
2813
2814 /*
2815 * SmartReflex sysc found on omap36xx and later
2816 */
2817 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2818 .dmadisable_shift = -ENODEV,
2819 .midle_shift = -ENODEV,
2820 .sidle_shift = 24,
2821 .clkact_shift = -ENODEV,
2822 .enwkup_shift = 26,
2823 .srst_shift = -ENODEV,
2824 .emufree_shift = -ENODEV,
2825 .autoidle_shift = -ENODEV,
2826 };
2827
2828 static const struct sysc_capabilities sysc_36xx_sr = {
2829 .type = TI_SYSC_OMAP36XX_SR,
2830 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2831 .regbits = &sysc_regbits_omap36xx_sr,
2832 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2833 };
2834
2835 static const struct sysc_capabilities sysc_omap4_sr = {
2836 .type = TI_SYSC_OMAP4_SR,
2837 .regbits = &sysc_regbits_omap36xx_sr,
2838 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2839 };
2840
2841 /*
2842 * McASP register bits found on omap4 and later
2843 */
2844 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2845 .dmadisable_shift = -ENODEV,
2846 .midle_shift = -ENODEV,
2847 .sidle_shift = 0,
2848 .clkact_shift = -ENODEV,
2849 .enwkup_shift = -ENODEV,
2850 .srst_shift = -ENODEV,
2851 .emufree_shift = -ENODEV,
2852 .autoidle_shift = -ENODEV,
2853 };
2854
2855 static const struct sysc_capabilities sysc_omap4_mcasp = {
2856 .type = TI_SYSC_OMAP4_MCASP,
2857 .regbits = &sysc_regbits_omap4_mcasp,
2858 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2859 };
2860
2861 /*
2862 * McASP found on dra7 and later
2863 */
2864 static const struct sysc_capabilities sysc_dra7_mcasp = {
2865 .type = TI_SYSC_OMAP4_SIMPLE,
2866 .regbits = &sysc_regbits_omap4_simple,
2867 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2868 };
2869
2870 /*
2871 * FS USB host found on omap4 and later
2872 */
2873 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2874 .dmadisable_shift = -ENODEV,
2875 .midle_shift = -ENODEV,
2876 .sidle_shift = 24,
2877 .clkact_shift = -ENODEV,
2878 .enwkup_shift = 26,
2879 .srst_shift = -ENODEV,
2880 .emufree_shift = -ENODEV,
2881 .autoidle_shift = -ENODEV,
2882 };
2883
2884 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2885 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2886 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2887 .regbits = &sysc_regbits_omap4_usb_host_fs,
2888 };
2889
2890 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2891 .dmadisable_shift = -ENODEV,
2892 .midle_shift = -ENODEV,
2893 .sidle_shift = -ENODEV,
2894 .clkact_shift = -ENODEV,
2895 .enwkup_shift = 4,
2896 .srst_shift = 0,
2897 .emufree_shift = -ENODEV,
2898 .autoidle_shift = -ENODEV,
2899 };
2900
2901 static const struct sysc_capabilities sysc_dra7_mcan = {
2902 .type = TI_SYSC_DRA7_MCAN,
2903 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2904 .regbits = &sysc_regbits_dra7_mcan,
2905 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2906 };
2907
2908 /*
2909 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2910 */
2911 static const struct sysc_capabilities sysc_pruss = {
2912 .type = TI_SYSC_PRUSS,
2913 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2914 .regbits = &sysc_regbits_omap4_simple,
2915 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2916 };
2917
sysc_init_pdata(struct sysc * ddata)2918 static int sysc_init_pdata(struct sysc *ddata)
2919 {
2920 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2921 struct ti_sysc_module_data *mdata;
2922
2923 if (!pdata)
2924 return 0;
2925
2926 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2927 if (!mdata)
2928 return -ENOMEM;
2929
2930 if (ddata->legacy_mode) {
2931 mdata->name = ddata->legacy_mode;
2932 mdata->module_pa = ddata->module_pa;
2933 mdata->module_size = ddata->module_size;
2934 mdata->offsets = ddata->offsets;
2935 mdata->nr_offsets = SYSC_MAX_REGS;
2936 mdata->cap = ddata->cap;
2937 mdata->cfg = &ddata->cfg;
2938 }
2939
2940 ddata->mdata = mdata;
2941
2942 return 0;
2943 }
2944
sysc_init_match(struct sysc * ddata)2945 static int sysc_init_match(struct sysc *ddata)
2946 {
2947 const struct sysc_capabilities *cap;
2948
2949 cap = of_device_get_match_data(ddata->dev);
2950 if (!cap)
2951 return -EINVAL;
2952
2953 ddata->cap = cap;
2954 if (ddata->cap)
2955 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2956
2957 return 0;
2958 }
2959
ti_sysc_idle(struct work_struct * work)2960 static void ti_sysc_idle(struct work_struct *work)
2961 {
2962 struct sysc *ddata;
2963
2964 ddata = container_of(work, struct sysc, idle_work.work);
2965
2966 /*
2967 * One time decrement of clock usage counts if left on from init.
2968 * Note that we disable opt clocks unconditionally in this case
2969 * as they are enabled unconditionally during init without
2970 * considering sysc_opt_clks_needed() at that point.
2971 */
2972 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2973 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2974 sysc_disable_main_clocks(ddata);
2975 sysc_disable_opt_clocks(ddata);
2976 sysc_clkdm_allow_idle(ddata);
2977 }
2978
2979 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2980 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2981 return;
2982
2983 /*
2984 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2985 * and SYSC_QUIRK_NO_RESET_ON_INIT
2986 */
2987 if (pm_runtime_active(ddata->dev))
2988 pm_runtime_put_sync(ddata->dev);
2989 }
2990
2991 /*
2992 * SoC model and features detection. Only needed for SoCs that need
2993 * special handling for quirks, no need to list others.
2994 */
2995 static const struct soc_device_attribute sysc_soc_match[] = {
2996 SOC_FLAG("OMAP242*", SOC_2420),
2997 SOC_FLAG("OMAP243*", SOC_2430),
2998 SOC_FLAG("AM35*", SOC_AM35),
2999 SOC_FLAG("OMAP3[45]*", SOC_3430),
3000 SOC_FLAG("OMAP3[67]*", SOC_3630),
3001 SOC_FLAG("OMAP443*", SOC_4430),
3002 SOC_FLAG("OMAP446*", SOC_4460),
3003 SOC_FLAG("OMAP447*", SOC_4470),
3004 SOC_FLAG("OMAP54*", SOC_5430),
3005 SOC_FLAG("AM433", SOC_AM3),
3006 SOC_FLAG("AM43*", SOC_AM4),
3007 SOC_FLAG("DRA7*", SOC_DRA7),
3008
3009 { /* sentinel */ },
3010 };
3011
3012 /*
3013 * List of SoCs variants with disabled features. By default we assume all
3014 * devices in the device tree are available so no need to list those SoCs.
3015 */
3016 static const struct soc_device_attribute sysc_soc_feat_match[] = {
3017 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
3018 SOC_FLAG("AM3505", DIS_SGX),
3019 SOC_FLAG("OMAP3525", DIS_SGX),
3020 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
3021 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
3022
3023 /* OMAP3630/DM3730 variants with some accelerators disabled */
3024 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
3025 SOC_FLAG("DM3725", DIS_SGX),
3026 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
3027 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
3028 SOC_FLAG("OMAP3621", DIS_ISP),
3029
3030 { /* sentinel */ },
3031 };
3032
sysc_add_disabled(unsigned long base)3033 static int sysc_add_disabled(unsigned long base)
3034 {
3035 struct sysc_address *disabled_module;
3036
3037 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
3038 if (!disabled_module)
3039 return -ENOMEM;
3040
3041 disabled_module->base = base;
3042
3043 mutex_lock(&sysc_soc->list_lock);
3044 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
3045 mutex_unlock(&sysc_soc->list_lock);
3046
3047 return 0;
3048 }
3049
3050 /*
3051 * One time init to detect the booted SoC, disable unavailable features
3052 * and initialize list for optional cpu_pm notifier.
3053 *
3054 * Note that we initialize static data shared across all ti-sysc instances
3055 * so ddata is only used for SoC type. This can be called from module_init
3056 * once we no longer need to rely on platform data.
3057 */
sysc_init_static_data(struct sysc * ddata)3058 static int sysc_init_static_data(struct sysc *ddata)
3059 {
3060 const struct soc_device_attribute *match;
3061 struct ti_sysc_platform_data *pdata;
3062 unsigned long features = 0;
3063 struct device_node *np;
3064
3065 if (sysc_soc)
3066 return 0;
3067
3068 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
3069 if (!sysc_soc)
3070 return -ENOMEM;
3071
3072 mutex_init(&sysc_soc->list_lock);
3073 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
3074 INIT_LIST_HEAD(&sysc_soc->restored_modules);
3075 sysc_soc->general_purpose = true;
3076
3077 pdata = dev_get_platdata(ddata->dev);
3078 if (pdata && pdata->soc_type_gp)
3079 sysc_soc->general_purpose = pdata->soc_type_gp();
3080
3081 match = soc_device_match(sysc_soc_match);
3082 if (match && match->data)
3083 sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
3084
3085 /*
3086 * Check and warn about possible old incomplete dtb. We now want to see
3087 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
3088 */
3089 switch (sysc_soc->soc) {
3090 case SOC_AM3:
3091 case SOC_AM4:
3092 case SOC_4430 ... SOC_4470:
3093 case SOC_5430:
3094 case SOC_DRA7:
3095 np = of_find_node_by_path("/ocp");
3096 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
3097 "ti-sysc: Incomplete old dtb, please update\n");
3098 break;
3099 default:
3100 break;
3101 }
3102
3103 /* Ignore devices that are not available on HS and EMU SoCs */
3104 if (!sysc_soc->general_purpose) {
3105 switch (sysc_soc->soc) {
3106 case SOC_3430 ... SOC_3630:
3107 sysc_add_disabled(0x48304000); /* timer12 */
3108 break;
3109 case SOC_AM3:
3110 sysc_add_disabled(0x48310000); /* rng */
3111 break;
3112 default:
3113 break;
3114 }
3115 }
3116
3117 match = soc_device_match(sysc_soc_feat_match);
3118 if (!match)
3119 return 0;
3120
3121 if (match->data)
3122 features = (unsigned long)match->data;
3123
3124 /*
3125 * Add disabled devices to the list based on the module base.
3126 * Note that this must be done before we attempt to access the
3127 * device and have module revision checks working.
3128 */
3129 if (features & DIS_ISP)
3130 sysc_add_disabled(0x480bd400);
3131 if (features & DIS_IVA)
3132 sysc_add_disabled(0x5d000000);
3133 if (features & DIS_SGX)
3134 sysc_add_disabled(0x50000000);
3135
3136 return 0;
3137 }
3138
sysc_cleanup_static_data(void)3139 static void sysc_cleanup_static_data(void)
3140 {
3141 struct sysc_module *restored_module;
3142 struct sysc_address *disabled_module;
3143 struct list_head *pos, *tmp;
3144
3145 if (!sysc_soc)
3146 return;
3147
3148 if (sysc_soc->nb.notifier_call)
3149 cpu_pm_unregister_notifier(&sysc_soc->nb);
3150
3151 mutex_lock(&sysc_soc->list_lock);
3152 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3153 restored_module = list_entry(pos, struct sysc_module, node);
3154 list_del(pos);
3155 kfree(restored_module);
3156 }
3157 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3158 disabled_module = list_entry(pos, struct sysc_address, node);
3159 list_del(pos);
3160 kfree(disabled_module);
3161 }
3162 mutex_unlock(&sysc_soc->list_lock);
3163 }
3164
sysc_check_disabled_devices(struct sysc * ddata)3165 static int sysc_check_disabled_devices(struct sysc *ddata)
3166 {
3167 struct sysc_address *disabled_module;
3168 struct list_head *pos;
3169 int error = 0;
3170
3171 mutex_lock(&sysc_soc->list_lock);
3172 list_for_each(pos, &sysc_soc->disabled_modules) {
3173 disabled_module = list_entry(pos, struct sysc_address, node);
3174 if (ddata->module_pa == disabled_module->base) {
3175 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3176 error = -ENODEV;
3177 break;
3178 }
3179 }
3180 mutex_unlock(&sysc_soc->list_lock);
3181
3182 return error;
3183 }
3184
3185 /*
3186 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3187 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3188 * are needed, we could also look at the timer register configuration.
3189 */
sysc_check_active_timer(struct sysc * ddata)3190 static int sysc_check_active_timer(struct sysc *ddata)
3191 {
3192 int error;
3193
3194 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3195 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3196 return 0;
3197
3198 /*
3199 * Quirk for omap3 beagleboard revision A to B4 to use gpt12.
3200 * Revision C and later are fixed with commit 23885389dbbb ("ARM:
3201 * dts: Fix timer regression for beagleboard revision c"). This all
3202 * can be dropped if we stop supporting old beagleboard revisions
3203 * A to B4 at some point.
3204 */
3205 if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35)
3206 error = -ENXIO;
3207 else
3208 error = -EBUSY;
3209
3210 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3211 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3212 return error;
3213
3214 return 0;
3215 }
3216
3217 static const struct of_device_id sysc_match_table[] = {
3218 { .compatible = "simple-bus", },
3219 { /* sentinel */ },
3220 };
3221
sysc_probe(struct platform_device * pdev)3222 static int sysc_probe(struct platform_device *pdev)
3223 {
3224 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3225 struct sysc *ddata;
3226 int error;
3227
3228 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3229 if (!ddata)
3230 return -ENOMEM;
3231
3232 ddata->offsets[SYSC_REVISION] = -ENODEV;
3233 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3234 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3235 ddata->dev = &pdev->dev;
3236 platform_set_drvdata(pdev, ddata);
3237
3238 error = sysc_init_static_data(ddata);
3239 if (error)
3240 return error;
3241
3242 error = sysc_init_match(ddata);
3243 if (error)
3244 return error;
3245
3246 error = sysc_init_dts_quirks(ddata);
3247 if (error)
3248 return error;
3249
3250 error = sysc_map_and_check_registers(ddata);
3251 if (error)
3252 return error;
3253
3254 error = sysc_init_sysc_mask(ddata);
3255 if (error)
3256 return error;
3257
3258 error = sysc_init_idlemodes(ddata);
3259 if (error)
3260 return error;
3261
3262 error = sysc_init_syss_mask(ddata);
3263 if (error)
3264 return error;
3265
3266 error = sysc_init_pdata(ddata);
3267 if (error)
3268 return error;
3269
3270 sysc_init_early_quirks(ddata);
3271
3272 error = sysc_check_disabled_devices(ddata);
3273 if (error)
3274 return error;
3275
3276 error = sysc_check_active_timer(ddata);
3277 if (error == -ENXIO)
3278 ddata->reserved = true;
3279 else if (error)
3280 return error;
3281
3282 error = sysc_get_clocks(ddata);
3283 if (error)
3284 return error;
3285
3286 error = sysc_init_resets(ddata);
3287 if (error)
3288 goto unprepare;
3289
3290 error = sysc_init_module(ddata);
3291 if (error)
3292 goto unprepare;
3293
3294 pm_runtime_enable(ddata->dev);
3295 error = pm_runtime_resume_and_get(ddata->dev);
3296 if (error < 0) {
3297 pm_runtime_disable(ddata->dev);
3298 goto unprepare;
3299 }
3300
3301 /* Balance use counts as PM runtime should have enabled these all */
3302 if (!(ddata->cfg.quirks &
3303 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3304 sysc_disable_main_clocks(ddata);
3305 sysc_disable_opt_clocks(ddata);
3306 sysc_clkdm_allow_idle(ddata);
3307 }
3308
3309 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3310 reset_control_assert(ddata->rsts);
3311
3312 sysc_show_registers(ddata);
3313
3314 ddata->dev->type = &sysc_device_type;
3315
3316 if (!ddata->reserved) {
3317 error = of_platform_populate(ddata->dev->of_node,
3318 sysc_match_table,
3319 pdata ? pdata->auxdata : NULL,
3320 ddata->dev);
3321 if (error)
3322 goto err;
3323 }
3324
3325 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3326
3327 /* At least earlycon won't survive without deferred idle */
3328 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3329 SYSC_QUIRK_NO_IDLE_ON_INIT |
3330 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3331 schedule_delayed_work(&ddata->idle_work, 3000);
3332 } else {
3333 pm_runtime_put(&pdev->dev);
3334 }
3335
3336 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3337 sysc_add_restored(ddata);
3338
3339 return 0;
3340
3341 err:
3342 pm_runtime_put_sync(&pdev->dev);
3343 pm_runtime_disable(&pdev->dev);
3344 unprepare:
3345 sysc_unprepare(ddata);
3346
3347 return error;
3348 }
3349
sysc_remove(struct platform_device * pdev)3350 static int sysc_remove(struct platform_device *pdev)
3351 {
3352 struct sysc *ddata = platform_get_drvdata(pdev);
3353 int error;
3354
3355 /* Device can still be enabled, see deferred idle quirk in probe */
3356 if (cancel_delayed_work_sync(&ddata->idle_work))
3357 ti_sysc_idle(&ddata->idle_work.work);
3358
3359 error = pm_runtime_resume_and_get(ddata->dev);
3360 if (error < 0) {
3361 pm_runtime_disable(ddata->dev);
3362 goto unprepare;
3363 }
3364
3365 of_platform_depopulate(&pdev->dev);
3366
3367 pm_runtime_put_sync(&pdev->dev);
3368 pm_runtime_disable(&pdev->dev);
3369
3370 if (!reset_control_status(ddata->rsts))
3371 reset_control_assert(ddata->rsts);
3372
3373 unprepare:
3374 sysc_unprepare(ddata);
3375
3376 return 0;
3377 }
3378
3379 static const struct of_device_id sysc_match[] = {
3380 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3381 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3382 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3383 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3384 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3385 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3386 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3387 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3388 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3389 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3390 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3391 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3392 { .compatible = "ti,sysc-usb-host-fs",
3393 .data = &sysc_omap4_usb_host_fs, },
3394 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3395 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3396 { },
3397 };
3398 MODULE_DEVICE_TABLE(of, sysc_match);
3399
3400 static struct platform_driver sysc_driver = {
3401 .probe = sysc_probe,
3402 .remove = sysc_remove,
3403 .driver = {
3404 .name = "ti-sysc",
3405 .of_match_table = sysc_match,
3406 .pm = &sysc_pm_ops,
3407 },
3408 };
3409
sysc_init(void)3410 static int __init sysc_init(void)
3411 {
3412 bus_register_notifier(&platform_bus_type, &sysc_nb);
3413
3414 return platform_driver_register(&sysc_driver);
3415 }
3416 module_init(sysc_init);
3417
sysc_exit(void)3418 static void __exit sysc_exit(void)
3419 {
3420 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3421 platform_driver_unregister(&sysc_driver);
3422 sysc_cleanup_static_data();
3423 }
3424 module_exit(sysc_exit);
3425
3426 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3427 MODULE_LICENSE("GPL v2");
3428