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Searched refs:U (Results 1 – 25 of 198) sorted by relevance

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/drivers/tty/vt/
Dcp437.uni16 0x00 U+0000
17 0x01 U+263a
18 0x02 U+263b
19 0x03 U+2665
20 0x04 U+2666 U+25c6
21 0x05 U+2663
22 0x06 U+2660
23 0x07 U+2022
24 0x08 U+25d8
25 0x09 U+25cb
[all …]
/drivers/comedi/drivers/ni_routing/ni_route_values/
Dni_eseries.c230 [B(NI_PFI(0))] = U(1),
231 [B(NI_PFI(1))] = U(2),
232 [B(NI_PFI(2))] = U(3),
233 [B(NI_PFI(3))] = U(4),
234 [B(NI_PFI(4))] = U(5),
235 [B(NI_PFI(5))] = U(6),
236 [B(NI_PFI(6))] = U(7),
237 [B(NI_PFI(7))] = U(8),
238 [B(NI_PFI(8))] = U(9),
239 [B(NI_PFI(9))] = U(10),
[all …]
Dni_660x.c122 [B(NI_PFI(11))] = U(9),
123 [B(NI_PFI(15))] = U(8),
124 [B(NI_PFI(19))] = U(7),
125 [B(NI_PFI(23))] = U(6),
126 [B(NI_PFI(27))] = U(5),
127 [B(NI_PFI(31))] = U(4),
128 [B(NI_PFI(35))] = U(3),
129 [B(NI_PFI(39))] = U(2 /* or 1 */),
130 [B(TRIGGER_LINE(0))] = U(11),
131 [B(TRIGGER_LINE(1))] = U(12),
[all …]
Dni_mseries.c810 [B(NI_PFI(0))] = U(1),
811 [B(NI_PFI(1))] = U(2),
812 [B(NI_PFI(2))] = U(3),
813 [B(NI_PFI(3))] = U(4),
814 [B(NI_PFI(4))] = U(5),
815 [B(NI_PFI(5))] = U(6),
816 [B(NI_PFI(6))] = U(7),
817 [B(NI_PFI(7))] = U(8),
818 [B(NI_PFI(8))] = U(9),
819 [B(NI_PFI(9))] = U(10),
[all …]
/drivers/media/i2c/ccs/
Dccs-regs.h24 #define CCS_PIXEL_ORDER_GRBG 0U
33 #define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
42 #define CCS_MODULE_DATE_PHASE_SHIFT 0U
44 #define CCS_MODULE_DATE_PHASE_TS 0U
58 #define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
63 #define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U
66 #define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U
82 #define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U
84 #define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U
101 #define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U
[all …]
/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_a0.c23 .irq_mask = ~0U, \
92 hw_atl_pci_pci_reg_res_dis_set(self, 0U); in hw_atl_a0_hw_reset()
93 hw_atl_rx_rx_reg_res_dis_set(self, 0U); in hw_atl_a0_hw_reset()
94 hw_atl_tx_tx_reg_res_dis_set(self, 0U); in hw_atl_a0_hw_reset()
106 hw_atl_itr_irq_reg_res_dis_set(self, 0U); in hw_atl_a0_hw_reset()
127 unsigned int i_priority = 0U; in hw_atl_a0_hw_qos_set()
128 u32 buff_size = 0U; in hw_atl_a0_hw_qos_set()
129 u32 tc = 0U; in hw_atl_a0_hw_qos_set()
136 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); in hw_atl_a0_hw_qos_set()
139 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); in hw_atl_a0_hw_qos_set()
[all …]
Dhw_atl_b0.c25 .irq_mask = ~0U, \
147 hw_atl_rpb_rx_xoff_en_per_tc_set(self, 0U, AQ_HW_PTP_TC); in hw_atl_b0_tc_ptp_set()
157 unsigned int prio = 0U; in hw_atl_b0_hw_qos_set()
158 u32 tc = 0U; in hw_atl_b0_hw_qos_set()
170 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); in hw_atl_b0_hw_qos_set()
175 u32 threshold = 0U; in hw_atl_b0_hw_qos_set()
213 unsigned int addr = 0U; in hw_atl_b0_hw_rss_hash_set()
214 unsigned int i = 0U; in hw_atl_b0_hw_rss_hash_set()
218 for (i = 10, addr = 0U; i--; ++addr) { in hw_atl_b0_hw_rss_hash_set()
220 __swab32(rss_params->hash_secret_key[i]) : 0U; in hw_atl_b0_hw_rss_hash_set()
[all …]
Dhw_atl_utils.c35 #define HW_ATL_MPI_STATE_SHIFT 0U
146 hw_atl_rx_rx_reg_res_dis_set(self, 0U); in hw_atl_utils_soft_reset_flb()
147 hw_atl_tx_tx_reg_res_dis_set(self, 0U); in hw_atl_utils_soft_reset_flb()
188 hw_atl_rx_rx_reg_res_dis_set(self, 0U); in hw_atl_utils_soft_reset_rbl()
189 hw_atl_tx_tx_reg_res_dis_set(self, 0U); in hw_atl_utils_soft_reset_rbl()
406 (val & 0x100) == 0U, in hw_atl_utils_write_b0_mbox()
479 unsigned int rnd = 0U; in hw_atl_utils_init_ucp()
480 unsigned int ucp_0x370 = 0U; in hw_atl_utils_init_ucp()
493 self->mbox_addr != 0U, in hw_atl_utils_init_ucp()
497 self->rpc_addr != 0U, in hw_atl_utils_init_ucp()
[all …]
Dhw_atl_llh.c242 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, in hw_atl_itr_irq_map_rx_set()
243 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, in hw_atl_itr_irq_map_rx_set()
244 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, in hw_atl_itr_irq_map_rx_set()
245 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U in hw_atl_itr_irq_map_rx_set()
818 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U in hw_atl_rpf_rpb_user_priority_tc_map_set()
1192 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, in hw_atl_rpo_lro_max_num_of_descriptors_set()
1193 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, in hw_atl_rpo_lro_max_num_of_descriptors_set()
1194 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, in hw_atl_rpo_lro_max_num_of_descriptors_set()
1195 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U in hw_atl_rpo_lro_max_num_of_descriptors_set()
1687 aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U); in hw_atl_rpfl3l4_ipv4_dest_addr_clear()
[all …]
Dhw_atl_b0_internal.h26 #define HW_ATL_B0_MAC 0U
82 #define HW_ATL_B0_RS_SLIP_ENABLED 0U
/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2.c26 .irq_mask = ~0U, \
167 unsigned int prio = 0U; in hw_atl2_hw_qos_set()
168 u32 tc = 0U; in hw_atl2_hw_qos_set()
175 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); in hw_atl2_hw_qos_set()
180 u32 threshold = 0U; in hw_atl2_hw_qos_set()
287 hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U); in hw_atl2_hw_init_tx_tc_rate_limit()
291 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); in hw_atl2_hw_init_tx_tc_rate_limit()
293 hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U); in hw_atl2_hw_init_tx_tc_rate_limit()
296 const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U; in hw_atl2_hw_init_tx_tc_rate_limit()
340 hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U); in hw_atl2_hw_init_tx_tc_rate_limit()
[all …]
/drivers/net/ethernet/aquantia/atlantic/
Daq_vec.c36 unsigned int sw_tail_old = 0U; in aq_vec_poll()
39 unsigned int i = 0U; in aq_vec_poll()
46 for (i = 0U; self->tx_rings > i; ++i) { in aq_vec_poll()
138 unsigned int i = 0U; in aq_vec_ring_alloc()
179 unsigned int i = 0U; in aq_vec_init()
185 for (i = 0U; self->tx_rings > i; ++i) { in aq_vec_init()
212 &ring[AQ_VEC_RX_ID], 0U); in aq_vec_init()
224 unsigned int i = 0U; in aq_vec_start()
227 for (i = 0U; self->tx_rings > i; ++i) { in aq_vec_start()
249 unsigned int i = 0U; in aq_vec_stop()
[all …]
Daq_cfg.h18 #define AQ_CFG_IS_POLLING_DEF 0U
20 #define AQ_CFG_FORCE_LEGACY_INT 0U
42 #define AQ_CFG_RX_PAGEORDER 0U
53 #define AQ_CFG_RSS_BASE_CPU_NUM_DEF 0U
Daq_nic.c133 cfg->is_rss = 0U; in aq_nic_cfg_start()
268 unsigned int i = 0U; in aq_nic_polling_timer_cb()
270 for (i = 0U; self->aq_vecs > i; ++i) in aq_nic_polling_timer_cb()
397 unsigned int i = 0U; in aq_nic_init()
431 for (i = 0U; i < self->aq_vecs; i++) { in aq_nic_init()
465 unsigned int i = 0U; in aq_nic_start()
481 for (i = 0U; self->aq_vecs > i; ++i) { in aq_nic_start()
512 for (i = 0U; self->aq_vecs > i; ++i) { in aq_nic_start()
574 unsigned int frag_count = 0U; in aq_nic_map_skb()
575 unsigned int ret = 0U; in aq_nic_map_skb()
[all …]
/drivers/gpu/drm/etnaviv/
Detnaviv_hwdb.c74 .product_id = ~0U,
75 .customer_id = ~0U,
105 .product_id = ~0U,
106 .customer_id = ~0U,
107 .eco_id = ~0U,
144 etnaviv_chip_identities[i].product_id == ~0U) && in etnaviv_fill_identity_from_hwdb()
146 etnaviv_chip_identities[i].customer_id == ~0U) && in etnaviv_fill_identity_from_hwdb()
148 etnaviv_chip_identities[i].eco_id == ~0U)) { in etnaviv_fill_identity_from_hwdb()
/drivers/media/pci/intel/ipu3/
Dipu3-cio2.h42 #define CIO2_PAD_SINK 0U
144 #define CIO2_INT_EXT_OE_DMAOE_SHIFT 0U
166 #define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT 0U
168 #define CIO2_PBM_ARB_CTRL_LANES_DIV 0U /* 4-4-2-2 lanes */
169 #define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT 0U
176 #define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT 0U
185 #define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT 0U
216 #define CIO2_LTRVAL02_VAL_SHIFT 0U
233 #define CIO2_CDMARI_FBPT_RP_SHIFT 0U
236 #define CIO2_CDMAC0_FBPT_LEN_SHIFT 0U
[all …]
/drivers/thunderbolt/
Dtest.c1918 KUNIT_EXPECT_EQ(test, path->hops[0].nfc_credits, 0U); in tb_test_credit_alloc_legacy_not_bonded()
1920 KUNIT_EXPECT_EQ(test, path->hops[1].nfc_credits, 0U); in tb_test_credit_alloc_legacy_not_bonded()
1925 KUNIT_EXPECT_EQ(test, path->hops[0].nfc_credits, 0U); in tb_test_credit_alloc_legacy_not_bonded()
1927 KUNIT_EXPECT_EQ(test, path->hops[1].nfc_credits, 0U); in tb_test_credit_alloc_legacy_not_bonded()
1951 KUNIT_EXPECT_EQ(test, path->hops[0].nfc_credits, 0U); in tb_test_credit_alloc_legacy_bonded()
1953 KUNIT_EXPECT_EQ(test, path->hops[1].nfc_credits, 0U); in tb_test_credit_alloc_legacy_bonded()
1958 KUNIT_EXPECT_EQ(test, path->hops[0].nfc_credits, 0U); in tb_test_credit_alloc_legacy_bonded()
1960 KUNIT_EXPECT_EQ(test, path->hops[1].nfc_credits, 0U); in tb_test_credit_alloc_legacy_bonded()
1984 KUNIT_EXPECT_EQ(test, path->hops[0].nfc_credits, 0U); in tb_test_credit_alloc_pcie()
1986 KUNIT_EXPECT_EQ(test, path->hops[1].nfc_credits, 0U); in tb_test_credit_alloc_pcie()
[all …]
/drivers/input/tablet/
DKconfig29 tristate "Aiptek 6000U/8000U and Genius G_PEN tablet support (USB)"
33 Say Y here if you want to use the USB version of the Aiptek 6000U,
34 Aiptek 8000U or Genius G-PEN 560 tablet. Make sure to say Y to
/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Ddisp.c32 struct bit_entry U; in nvbios_disp_table() local
34 if (!bit_entry(bios, 'U', &U)) { in nvbios_disp_table()
35 if (U.version == 1) { in nvbios_disp_table()
36 u16 data = nvbios_rd16(bios, U.offset); in nvbios_disp_table()
/drivers/comedi/drivers/ni_routing/
Dni_route_values.h45 #define U(x) 0x0 macro
52 #define U(x) (((x) & 0x7f) | 0x200) macro
/drivers/scsi/snic/
Dvnic_devcmd.h39 #define _CMD_DIR_NONE 0U
47 #define _CMD_FLAGS_NONE 0U
53 #define _CMD_VTYPE_NONE 0U
/drivers/remoteproc/
Dst_slim_rproc.c131 writel(~0U, slim_rproc->peri + SLIM_INT_CLR_OFST); in slim_rproc_start()
132 writel(~0U, slim_rproc->peri + SLIM_CMD_CLR_OFST); in slim_rproc_start()
135 writel(~0U, slim_rproc->peri + SLIM_INT_MASK_OFST); in slim_rproc_start()
136 writel(~0U, slim_rproc->peri + SLIM_CMD_MASK_OFST); in slim_rproc_start()
/drivers/staging/media/ipu3/
Dipu3.h38 #define IPU3_INPUT_MIN_WIDTH 0U
39 #define IPU3_INPUT_MIN_HEIGHT 0U
/drivers/scsi/fnic/
Dvnic_devcmd.h39 #define _CMD_DIR_NONE 0U
47 #define _CMD_FLAGS_NONE 0U
53 #define _CMD_VTYPE_NONE 0U
/drivers/md/bcache/
Dbcache_ondisk.h287 #define CACHE_REPLACEMENT_LRU 0U
292 #define CACHE_MODE_WRITETHROUGH 0U
297 #define BDEV_STATE_NONE 0U

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