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Searched refs:UVD0_BASE__INST5_SEG2 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/
Dcyan_skillfish_ip_offset.h709 #define UVD0_BASE__INST5_SEG2 0 macro
Dnavi12_ip_offset.h1109 #define UVD0_BASE__INST5_SEG2 0 macro
Dnavi14_ip_offset.h1109 #define UVD0_BASE__INST5_SEG2 0 macro
Drenoir_ip_offset.h1359 #define UVD0_BASE__INST5_SEG2 0 macro