| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 221 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gfxhub_v1_0_enable_system_domain()
222 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in gfxhub_v1_0_enable_system_domain()
224 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in gfxhub_v1_0_enable_system_domain()
226 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in gfxhub_v1_0_enable_system_domain()
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| D | mmhub_v1_0.c | 202 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_0_enable_system_domain()
203 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in mmhub_v1_0_enable_system_domain()
204 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in mmhub_v1_0_enable_system_domain()
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| D | mmhub_v1_7.c | 231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in mmhub_v1_7_enable_system_domain()
232 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, in mmhub_v1_7_enable_system_domain()
234 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, in mmhub_v1_7_enable_system_domain()
236 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, in mmhub_v1_7_enable_system_domain()
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| D | gmc_v7_0.c | 666 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
667 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v7_0_gart_enable()
668 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v7_0_gart_enable()
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| D | gmc_v8_0.c | 905 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
906 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
907 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
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| D | sid.h | 393 #define VM_CONTEXT0_CNTL 0x504 macro
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| /drivers/gpu/drm/radeon/ |
| D | rv770.c | 939 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
944 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_enable()
961 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_pcie_gart_disable()
1012 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in rv770_agp_enable()
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| D | rv770d.h | 634 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | ni.c | 1298 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1355 WREG32(VM_CONTEXT0_CNTL, 0); in cayman_pcie_gart_disable()
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| D | nid.h | 127 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | r600.c | 1171 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
1176 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_enable()
1193 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_disable()
1259 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_agp_enable()
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| D | sid.h | 392 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | cikd.h | 510 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | evergreen.c | 2442 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
2461 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_pcie_gart_disable()
2511 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_agp_enable()
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| D | evergreend.h | 1136 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | r600d.h | 573 #define VM_CONTEXT0_CNTL 0x1410 macro
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| D | si.c | 4321 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4386 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
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| D | cik.c | 5456 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5550 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
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