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Searched refs:WREG32_RLC (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v9.c106 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
107 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
256 WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); in kgd_gfx_v9_hqd_load()
262 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_gfx_v9_hqd_load()
291 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_hqd_load()
293 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_hqd_load()
295 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_gfx_v9_hqd_load()
297 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_gfx_v9_hqd_load()
304 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), in kgd_gfx_v9_hqd_load()
309 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); in kgd_gfx_v9_hqd_load()
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Dsoc15_common.h102 #define WREG32_RLC(reg, value) \ macro
Dsoc15.c516 WREG32_RLC(reg, tmp); in soc15_program_register_sequence()
Dgfx_v9_0.c2727 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), in gfx_v9_0_init_csb()
2729 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), in gfx_v9_0_init_csb()
2731 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), in gfx_v9_0_init_csb()