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Searched refs:X16CLK (Results 1 – 10 of 10) sorted by relevance

/drivers/net/hamradio/
Dz8530.h83 #define X16CLK 0x40 /* x16 clock mode */ macro
/drivers/tty/serial/
Dzs.h136 #define X16CLK 0x40 /* x16 clock mode */ macro
Dsunzilog.h109 #define X16CLK 0x40 /* x16 clock mode */ macro
Dip22zilog.h117 #define X16CLK 0x40 /* x16 clock mode */ macro
Dpmac_zilog.h207 #define X16CLK 0x40 /* x16 clock mode */ macro
Dpmac_zilog.c813 write_zsreg(uap, 4, X16CLK | SB_MASK); in pmz_fix_zero_bug_scc()
857 uap->curregs[R4] = X16CLK | SB1; in __pmz_startup()
1016 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()
1026 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()
Dsunzilog.c874 up->curregs[R4] |= X16CLK; in sunzilog_convert_to_zs()
1348 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; in sunzilog_init_hw()
1364 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; in sunzilog_init_hw()
Dip22zilog.c809 up->curregs[R4] |= X16CLK; in ip22zilog_convert_to_zs()
1141 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; in ip22zilog_prepare()
Dzs.c113 X16CLK | SB1, /* write 4 */
902 zport->regs[4] |= X16CLK; in zs_set_termios()
/drivers/net/wan/
Dz85230.h104 #define X16CLK 0x40 /* x16 clock mode */ macro