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Searched refs:__reg (Results 1 – 20 of 20) sorted by relevance

/drivers/net/wireless/ralink/rt2x00/
Drt2x00reg.h235 #define SET_FIELD(__reg, __type, __field, __value)\ argument
238 *(__reg) &= ~((__field).bit_mask); \
239 *(__reg) |= ((__value) << \
244 #define GET_FIELD(__reg, __type, __field) \ argument
247 ((__reg) & ((__field).bit_mask)) >> \
251 #define rt2x00_set_field32(__reg, __field, __value) \ argument
252 SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
253 #define rt2x00_get_field32(__reg, __field) \ argument
254 GET_FIELD(__reg, struct rt2x00_field32, __field)
256 #define rt2x00_set_field16(__reg, __field, __value) \ argument
[all …]
Drt2500usb.c117 #define WAIT_FOR_BBP(__dev, __reg) \ argument
118 rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
119 #define WAIT_FOR_RF(__dev, __reg) \ argument
120 rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
Drt2400pci.c40 #define WAIT_FOR_BBP(__dev, __reg) \ argument
41 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
42 #define WAIT_FOR_RF(__dev, __reg) \ argument
43 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
Drt61pci.c46 #define WAIT_FOR_BBP(__dev, __reg) \ argument
47 rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
48 #define WAIT_FOR_RF(__dev, __reg) \ argument
49 rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
50 #define WAIT_FOR_MCU(__dev, __reg) \ argument
52 H2M_MAILBOX_CSR_OWNER, (__reg))
Drt2500pci.c40 #define WAIT_FOR_BBP(__dev, __reg) \ argument
41 rt2x00mmio_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
42 #define WAIT_FOR_RF(__dev, __reg) \ argument
43 rt2x00mmio_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
Drt73usb.c47 #define WAIT_FOR_BBP(__dev, __reg) \ argument
48 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
49 #define WAIT_FOR_RF(__dev, __reg) \ argument
50 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
Drt2800lib.c51 #define WAIT_FOR_BBP(__dev, __reg) \ argument
52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
53 #define WAIT_FOR_RFCSR(__dev, __reg) \ argument
54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ argument
57 (__reg))
58 #define WAIT_FOR_RF(__dev, __reg) \ argument
59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
60 #define WAIT_FOR_MCU(__dev, __reg) \ argument
62 H2M_MAILBOX_CSR_OWNER, (__reg))
/drivers/soc/amlogic/
Dmeson-ee-pwrc.c111 #define VPU_MEMPD(__reg) \ argument
112 { __reg, GENMASK(1, 0) }, \
113 { __reg, GENMASK(3, 2) }, \
114 { __reg, GENMASK(5, 4) }, \
115 { __reg, GENMASK(7, 6) }, \
116 { __reg, GENMASK(9, 8) }, \
117 { __reg, GENMASK(11, 10) }, \
118 { __reg, GENMASK(13, 12) }, \
119 { __reg, GENMASK(15, 14) }, \
120 { __reg, GENMASK(17, 16) }, \
[all …]
/drivers/mmc/host/
Ddw_mmc.h459 #define mci_fifo_readw(__reg) __raw_readw(__reg) argument
460 #define mci_fifo_readl(__reg) __raw_readl(__reg) argument
461 #define mci_fifo_readq(__reg) __raw_readq(__reg) argument
463 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) argument
464 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) argument
465 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) argument
499 #define __raw_writeq(__value, __reg) \ argument
500 (*(volatile u64 __force *)(__reg) = (__value))
501 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) argument
/drivers/gpu/drm/armada/
Darmada_crtc.h20 struct armada_regs *__reg = _r; \
21 __reg[_i].offset = _o; \
22 __reg[_i].mask = ~(_m); \
23 __reg[_i].val = _v; \
/drivers/media/dvb-frontends/
Dstv090x_priv.h37 #define STV090x_READ_DEMOD(__state, __reg) (( \ argument
39 stv090x_read_reg(__state, STV090x_P2_##__reg) : \
40 stv090x_read_reg(__state, STV090x_P1_##__reg))
42 #define STV090x_WRITE_DEMOD(__state, __reg, __data) (( \ argument
44 stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\
45 stv090x_write_reg(__state, STV090x_P1_##__reg, __data))
/drivers/clk/microchip/
Dclk-pic32mzda.c27 #define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags) \ argument
29 .ctrl_reg = (__reg), \
41 #define DECLARE_REFO_CLOCK(__clkid, __reg) \ argument
43 .ctrl_reg = (__reg), \
/drivers/fsi/
Dfsi-master-hub.c200 __be32 __reg; in hub_master_probe() local
203 rc = fsi_device_read(fsi_dev, FSI_MVER, &__reg, sizeof(__reg)); in hub_master_probe()
207 reg = be32_to_cpu(__reg); in hub_master_probe()
/drivers/net/ethernet/qlogic/qed/
Dqed_init_fw_funcs.c162 u32 __reg = 0; \
164 BUILD_BUG_ON(sizeof((map).reg) != sizeof(__reg)); \
166 SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); \
167 SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_RL_VALID, \
169 SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, (vp_pq_id)); \
170 SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_RL_ID, (rl_id)); \
171 SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_VOQ, (ext_voq)); \
172 SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, \
176 __reg); \
177 (map).reg = cpu_to_le32(__reg); \
/drivers/net/ethernet/cadence/
Dmacb.h773 #define macb_or_gem_writel(__bp, __reg, __value) \ argument
776 gem_writel((__bp), __reg, __value); \
778 macb_writel((__bp), __reg, __value); \
781 #define macb_or_gem_readl(__bp, __reg) \ argument
785 __v = gem_readl((__bp), __reg); \
787 __v = macb_readl((__bp), __reg); \
/drivers/media/platform/s3c-camif/
Dcamif-regs.h159 #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3) argument
/drivers/pinctrl/spear/
Dpinctrl-plgpio.c637 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ argument
639 _tmp = readl_relaxed(plgpio->regs.__reg + _off); \
641 plgpio->csave_regs[i].__reg = \
642 _tmp | (plgpio->csave_regs[i].__reg & _mask); \
/drivers/net/ethernet/smsc/
Dsmc91x.h35 unsigned int __reg = (r); \
36 SMC_outb(__val16, a, __reg); \
37 SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
43 unsigned int __reg = r; \
44 __val16 = SMC_inb(a, __reg); \
45 __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
/drivers/net/ethernet/sun/
Dsunhme.c244 #define hme_write32(__hp, __reg, __val) \ argument
245 ((__hp)->write32((__reg), (__val)))
246 #define hme_read32(__hp, __reg) \ argument
247 ((__hp)->read32(__reg))
257 #define hme_write32(__hp, __reg, __val) \ argument
258 sbus_writel((__val), (__reg))
259 #define hme_read32(__hp, __reg) \ argument
260 sbus_readl(__reg)
274 #define hme_write32(__hp, __reg, __val) \ argument
275 writel((__val), (__reg))
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/drivers/hwmon/
Dadt7411.c199 #define ADT7411_BIT_ATTR(__name, __reg, __bit) \ argument
201 adt7411_set_bit, __bit, __reg)