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Searched refs:adjusted_pix_clk_100hz (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c208 pll_settings->adjusted_pix_clk_100hz, in calc_fb_divider_checking_tolerance()
227 pll_settings->adjusted_pix_clk_100hz) in calc_fb_divider_checking_tolerance()
229 pll_settings->adjusted_pix_clk_100hz in calc_fb_divider_checking_tolerance()
230 : pll_settings->adjusted_pix_clk_100hz - in calc_fb_divider_checking_tolerance()
264 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / in calc_pll_dividers_in_range()
301 if (pll_settings->adjusted_pix_clk_100hz == 0) { in calculate_pixel_clock_pll_dividers()
313 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < in calculate_pixel_clock_pll_dividers()
316 pll_settings->adjusted_pix_clk_100hz; in calculate_pixel_clock_pll_dividers()
318 pll_settings->adjusted_pix_clk_100hz) < in calculate_pixel_clock_pll_dividers()
324 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz in calculate_pixel_clock_pll_dividers()
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c622 int adjusted_pix_clk_100hz) in dcn10_link_encoder_validate_hdmi_output() argument
629 adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000) in dcn10_link_encoder_validate_hdmi_output()
637 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) in dcn10_link_encoder_validate_hdmi_output()
640 if ((adjusted_pix_clk_100hz == 0) || in dcn10_link_encoder_validate_hdmi_output()
641 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) in dcn10_link_encoder_validate_hdmi_output()
650 adjusted_pix_clk_100hz >= 3000000) in dcn10_link_encoder_validate_hdmi_output()
/drivers/gpu/drm/amd/display/dc/inc/
Dclock_source.h108 uint32_t adjusted_pix_clk_100hz; member