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Searched refs:aq (Results 1 – 25 of 42) sorted by relevance

12

/drivers/s390/crypto/
Dap_queue.c19 static void __ap_flush_queue(struct ap_queue *aq);
30 static int ap_queue_enable_irq(struct ap_queue *aq, void *ind) in ap_queue_enable_irq() argument
37 status = ap_aqic(aq->qid, qirqctrl, ind); in ap_queue_enable_irq()
47 AP_QID_CARD(aq->qid), in ap_queue_enable_irq()
48 AP_QID_QUEUE(aq->qid)); in ap_queue_enable_irq()
122 static enum ap_sm_wait ap_sm_nop(struct ap_queue *aq) in ap_sm_nop() argument
134 static struct ap_queue_status ap_sm_recv(struct ap_queue *aq) in ap_sm_recv() argument
151 status = ap_dqap(aq->qid, &aq->reply->psmid, in ap_sm_recv()
152 aq->reply->msg, aq->reply->bufsize, in ap_sm_recv()
159 aq->queue_count = max_t(int, 0, aq->queue_count - 1); in ap_sm_recv()
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Dap_bus.c419 struct ap_queue *aq = from_timer(aq, t, timeout); in ap_request_timeout() local
421 spin_lock_bh(&aq->lock); in ap_request_timeout()
422 ap_wait(ap_sm_event(aq, AP_SM_EVENT_TIMEOUT)); in ap_request_timeout()
423 spin_unlock_bh(&aq->lock); in ap_request_timeout()
458 struct ap_queue *aq; in ap_tasklet_fn() local
469 hash_for_each(ap_queues, bkt, aq, hnode) { in ap_tasklet_fn()
470 spin_lock_bh(&aq->lock); in ap_tasklet_fn()
471 wait = min(wait, ap_sm_event_loop(aq, AP_SM_EVENT_POLL)); in ap_tasklet_fn()
472 spin_unlock_bh(&aq->lock); in ap_tasklet_fn()
482 struct ap_queue *aq; in ap_pending_requests() local
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Dap_card.c81 struct ap_queue *aq; in request_count_store() local
85 hash_for_each(ap_queues, bkt, aq, hnode) in request_count_store()
86 if (ac == aq->card) in request_count_store()
87 aq->total_request_count = 0; in request_count_store()
100 struct ap_queue *aq; in requestq_count_show() local
106 hash_for_each(ap_queues, bkt, aq, hnode) in requestq_count_show()
107 if (ac == aq->card) in requestq_count_show()
108 reqq_cnt += aq->requestq_count; in requestq_count_show()
119 struct ap_queue *aq; in pendingq_count_show() local
125 hash_for_each(ap_queues, bkt, aq, hnode) in pendingq_count_show()
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Dzcrypt_cex2c.c181 static int zcrypt_cex2c_rng_supported(struct ap_queue *aq) in zcrypt_cex2c_rng_supported() argument
210 msg->cprbx.domain = AP_QID_QUEUE(aq->qid); in zcrypt_cex2c_rng_supported()
212 rc = ap_send(aq->qid, 0x0102030405060708ULL, ap_msg.msg, ap_msg.len); in zcrypt_cex2c_rng_supported()
219 rc = ap_recv(aq->qid, &psmid, ap_msg.msg, 4096); in zcrypt_cex2c_rng_supported()
335 struct ap_queue *aq = to_ap_queue(&ap_dev->device); in zcrypt_cex2c_queue_probe() local
342 zq->queue = aq; in zcrypt_cex2c_queue_probe()
345 ap_rapq(aq->qid); in zcrypt_cex2c_queue_probe()
346 rc = zcrypt_cex2c_rng_supported(aq); in zcrypt_cex2c_queue_probe()
357 ap_queue_init_state(aq); in zcrypt_cex2c_queue_probe()
358 ap_queue_init_reply(aq, &zq->reply); in zcrypt_cex2c_queue_probe()
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Dap_bus.h268 enum ap_sm_wait ap_sm_event(struct ap_queue *aq, enum ap_sm_event event);
269 enum ap_sm_wait ap_sm_event_loop(struct ap_queue *aq, enum ap_sm_event event);
271 int ap_queue_message(struct ap_queue *aq, struct ap_message *ap_msg);
272 void ap_cancel_message(struct ap_queue *aq, struct ap_message *ap_msg);
273 void ap_flush_queue(struct ap_queue *aq);
283 void ap_queue_init_reply(struct ap_queue *aq, struct ap_message *ap_msg);
285 void ap_queue_prepare_remove(struct ap_queue *aq);
286 void ap_queue_remove(struct ap_queue *aq);
287 void ap_queue_init_state(struct ap_queue *aq);
Dzcrypt_cex4.c597 struct ap_queue *aq = to_ap_queue(&ap_dev->device); in zcrypt_cex4_queue_probe() local
601 if (ap_test_bit(&aq->card->functions, AP_FUNC_ACCEL)) { in zcrypt_cex4_queue_probe()
602 zq = zcrypt_queue_alloc(aq->card->maxmsgsize); in zcrypt_cex4_queue_probe()
607 } else if (ap_test_bit(&aq->card->functions, AP_FUNC_COPRO)) { in zcrypt_cex4_queue_probe()
608 zq = zcrypt_queue_alloc(aq->card->maxmsgsize); in zcrypt_cex4_queue_probe()
613 } else if (ap_test_bit(&aq->card->functions, AP_FUNC_EP11)) { in zcrypt_cex4_queue_probe()
614 zq = zcrypt_queue_alloc(aq->card->maxmsgsize); in zcrypt_cex4_queue_probe()
623 zq->queue = aq; in zcrypt_cex4_queue_probe()
626 ap_queue_init_state(aq); in zcrypt_cex4_queue_probe()
627 ap_queue_init_reply(aq, &zq->reply); in zcrypt_cex4_queue_probe()
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Dzcrypt_queue.c44 struct ap_queue *aq = to_ap_queue(dev); in online_show() local
45 int online = aq->config && zq->online ? 1 : 0; in online_show()
55 struct ap_queue *aq = to_ap_queue(dev); in online_store() local
62 if (online && (!aq->config || !aq->card->config)) in online_store()
73 ap_send_online_uevent(&aq->ap_dev, online); in online_store()
Dzcrypt_cex2a.c152 struct ap_queue *aq = to_ap_queue(&ap_dev->device); in zcrypt_cex2a_queue_probe() local
171 zq->queue = aq; in zcrypt_cex2a_queue_probe()
174 ap_queue_init_state(aq); in zcrypt_cex2a_queue_probe()
175 ap_queue_init_reply(aq, &zq->reply); in zcrypt_cex2a_queue_probe()
176 aq->request_timeout = CEX2A_CLEANUP_TIME; in zcrypt_cex2a_queue_probe()
/drivers/net/ethernet/intel/i40e/
Di40e_adminq.c22 hw->aq.asq.tail = I40E_VF_ATQT1; in i40e_adminq_init_regs()
23 hw->aq.asq.head = I40E_VF_ATQH1; in i40e_adminq_init_regs()
24 hw->aq.asq.len = I40E_VF_ATQLEN1; in i40e_adminq_init_regs()
25 hw->aq.asq.bal = I40E_VF_ATQBAL1; in i40e_adminq_init_regs()
26 hw->aq.asq.bah = I40E_VF_ATQBAH1; in i40e_adminq_init_regs()
27 hw->aq.arq.tail = I40E_VF_ARQT1; in i40e_adminq_init_regs()
28 hw->aq.arq.head = I40E_VF_ARQH1; in i40e_adminq_init_regs()
29 hw->aq.arq.len = I40E_VF_ARQLEN1; in i40e_adminq_init_regs()
30 hw->aq.arq.bal = I40E_VF_ARQBAL1; in i40e_adminq_init_regs()
31 hw->aq.arq.bah = I40E_VF_ARQBAH1; in i40e_adminq_init_regs()
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Di40e_nvm.c76 access, time_left, ret_code, hw->aq.asq_last_status); in i40e_acquire_nvm()
98 time_left, ret_code, hw->aq.asq_last_status); in i40e_acquire_nvm()
126 (total_delay < hw->aq.asq_cmd_timeout)) { in i40e_release_nvm()
873 mutex_lock(&hw->aq.arq_mutex); in i40e_nvmupd_command()
911 mutex_unlock(&hw->aq.arq_mutex); in i40e_nvmupd_command()
939 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
950 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
964 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
981 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
998 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
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Di40e_main.c1815 i40e_aq_str(hw, hw->aq.asq_last_status)); in i40e_set_mac()
1847 i40e_aq_str(hw, hw->aq.asq_last_status)); in i40e_config_rss_aq()
1859 i40e_aq_str(hw, hw->aq.asq_last_status)); in i40e_config_rss_aq()
2343 aq_err = hw->aq.asq_last_status; in i40e_aqc_del_filters()
2377 aq_err = hw->aq.asq_last_status; in i40e_aqc_add_filters()
2437 i40e_aq_str(hw, hw->aq.asq_last_status), in i40e_aqc_broadcast_filter()
2479 i40e_aq_str(hw, hw->aq.asq_last_status)); in i40e_set_promiscuous()
2491 i40e_aq_str(hw, hw->aq.asq_last_status)); in i40e_set_promiscuous()
2501 i40e_aq_str(hw, hw->aq.asq_last_status)); in i40e_set_promiscuous()
2620 filter_list_len = hw->aq.asq_buf_size / in i40e_sync_vsi_filters()
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Di40e_debugfs.c506 ring = &(hw->aq.asq); in i40e_dbg_dump_aq_desc()
519 ring = &(hw->aq.arq); in i40e_dbg_dump_aq_desc()
1062 pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
1175 ret, pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
1315 desc->opcode, pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
1376 desc->opcode, pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
1408 pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
1419 __func__, pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
1437 __func__, pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
1445 pf->hw.aq.asq_last_status); in i40e_dbg_command_write()
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Di40e_client.c357 cdev->lan_info.fw_maj_ver = pf->hw.aq.fw_maj_ver; in i40e_client_add_instance()
358 cdev->lan_info.fw_min_ver = pf->hw.aq.fw_min_ver; in i40e_client_add_instance()
359 cdev->lan_info.fw_build = pf->hw.aq.fw_build; in i40e_client_add_instance()
550 err, hw->aq.asq_last_status); in i40e_client_virtchnl_send()
692 pf->hw.aq.asq_last_status)); in i40e_client_update_vsi_ctxt()
720 pf->hw.aq.asq_last_status)); in i40e_client_update_vsi_ctxt()
Di40e_common.c193 if (hw->aq.asq.len) in i40e_check_asq_alive()
194 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
1340 switch (hw->aq.asq_last_status) { in i40e_aq_get_phy_capabilities()
1354 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && in i40e_aq_get_phy_capabilities()
1362 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && in i40e_aq_get_phy_capabilities()
1363 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { in i40e_aq_get_phy_capabilities()
1634 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && in i40e_aq_get_link_info()
1635 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) in i40e_aq_get_link_info()
1719 static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj, in i40e_is_aq_api_ver_ge() argument
1722 return (aq->api_maj_ver > maj || in i40e_is_aq_api_ver_ge()
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Di40e_dcb.c787 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) in i40e_get_ieee_dcb_config()
808 (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) || in i40e_get_dcb_config()
809 (hw->aq.fw_maj_ver < 4))) in i40e_get_dcb_config()
814 ((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver == 33))) { in i40e_get_dcb_config()
839 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) in i40e_get_dcb_config()
856 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) in i40e_get_dcb_config()
965 } else if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) { in i40e_get_fw_lldp_status()
969 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EPERM) { in i40e_get_fw_lldp_status()
/drivers/net/ethernet/intel/iavf/
Diavf_adminq.c19 hw->aq.asq.tail = IAVF_VF_ATQT1; in iavf_adminq_init_regs()
20 hw->aq.asq.head = IAVF_VF_ATQH1; in iavf_adminq_init_regs()
21 hw->aq.asq.len = IAVF_VF_ATQLEN1; in iavf_adminq_init_regs()
22 hw->aq.asq.bal = IAVF_VF_ATQBAL1; in iavf_adminq_init_regs()
23 hw->aq.asq.bah = IAVF_VF_ATQBAH1; in iavf_adminq_init_regs()
24 hw->aq.arq.tail = IAVF_VF_ARQT1; in iavf_adminq_init_regs()
25 hw->aq.arq.head = IAVF_VF_ARQH1; in iavf_adminq_init_regs()
26 hw->aq.arq.len = IAVF_VF_ARQLEN1; in iavf_adminq_init_regs()
27 hw->aq.arq.bal = IAVF_VF_ARQBAL1; in iavf_adminq_init_regs()
28 hw->aq.arq.bah = IAVF_VF_ARQBAH1; in iavf_adminq_init_regs()
[all …]
Diavf_client.c150 err, adapter->hw.aq.asq_last_status); in iavf_client_release_qvlist()
432 err, adapter->hw.aq.asq_last_status); in iavf_client_virtchnl_send()
483 err, adapter->hw.aq.asq_last_status); in iavf_client_setup_qvlist()
/drivers/infiniband/hw/efa/
Defa_com.c118 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init_sq() local
119 struct efa_com_admin_sq *sq = &aq->sq; in efa_com_admin_init_sq()
120 u16 size = aq->depth * sizeof(*sq->entries); in efa_com_admin_init_sq()
126 dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL); in efa_com_admin_init_sq()
144 EFA_SET(&aq_caps, EFA_REGS_AQ_CAPS_AQ_DEPTH, aq->depth); in efa_com_admin_init_sq()
155 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init_cq() local
156 struct efa_com_admin_cq *cq = &aq->cq; in efa_com_admin_init_cq()
157 u16 size = aq->depth * sizeof(*cq->entries); in efa_com_admin_init_cq()
163 dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL); in efa_com_admin_init_cq()
178 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_DEPTH, aq->depth); in efa_com_admin_init_cq()
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Defa_com_cmd.c21 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_create_qp() local
41 err = efa_com_cmd_exec(aq, in efa_com_create_qp()
66 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_modify_qp() local
81 err = efa_com_cmd_exec(aq, in efa_com_modify_qp()
101 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_query_qp() local
109 err = efa_com_cmd_exec(aq, in efa_com_query_qp()
135 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_destroy_qp() local
141 err = efa_com_cmd_exec(aq, in efa_com_destroy_qp()
162 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_create_cq() local
177 err = efa_com_cmd_exec(aq, in efa_com_create_cq()
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Defa_com.h104 struct efa_com_admin_queue aq; member
137 int efa_com_cmd_exec(struct efa_com_admin_queue *aq,
/drivers/net/ethernet/marvell/octeontx2/nic/
Dcn10k.c77 struct nix_cn10k_aq_enq_req *aq; in cn10k_sq_aq_init() local
81 aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); in cn10k_sq_aq_init()
82 if (!aq) in cn10k_sq_aq_init()
85 aq->sq.cq = pfvf->hw.rx_queues + qidx; in cn10k_sq_aq_init()
86 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ in cn10k_sq_aq_init()
87 aq->sq.cq_ena = 1; in cn10k_sq_aq_init()
88 aq->sq.ena = 1; in cn10k_sq_aq_init()
90 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; in cn10k_sq_aq_init()
91 aq->sq.smq_rr_weight = mtu_to_dwrr_weight(pfvf, pfvf->max_frs); in cn10k_sq_aq_init()
92 aq->sq.default_chan = pfvf->hw.tx_chan_base; in cn10k_sq_aq_init()
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Dotx2_common.c307 struct nix_aq_enq_req *aq; in otx2_set_rss_table() local
314 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); in otx2_set_rss_table()
315 if (!aq) { in otx2_set_rss_table()
324 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); in otx2_set_rss_table()
325 if (!aq) { in otx2_set_rss_table()
331 aq->rss.rq = rss_ctx->ind_tbl[idx]; in otx2_set_rss_table()
334 aq->qidx = index + idx; in otx2_set_rss_table()
335 aq->ctype = NIX_AQ_CTYPE_RSS; in otx2_set_rss_table()
336 aq->op = NIX_AQ_INSTOP_INIT; in otx2_set_rss_table()
762 struct nix_aq_enq_req *aq; in otx2_rq_init() local
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/drivers/spi/
Datmel-quadspi.c225 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset) in atmel_qspi_read() argument
227 u32 value = readl_relaxed(aq->regs + offset); in atmel_qspi_read()
232 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value, in atmel_qspi_read()
239 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) in atmel_qspi_write() argument
244 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value, in atmel_qspi_write()
248 writel_relaxed(value, aq->regs + offset); in atmel_qspi_write()
300 static int atmel_qspi_set_cfg(struct atmel_qspi *aq, in atmel_qspi_set_cfg() argument
383 if (aq->mr != QSPI_MR_SMM) { in atmel_qspi_set_cfg()
384 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); in atmel_qspi_set_cfg()
385 aq->mr = QSPI_MR_SMM; in atmel_qspi_set_cfg()
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/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_npa.c18 struct admin_queue *aq = block->aq; in npa_aq_enqueue_wait() local
23 result = (struct npa_aq_res_s *)aq->res->base; in npa_aq_enqueue_wait()
29 memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)), in npa_aq_enqueue_wait()
30 (void *)inst, aq->inst->entry_sz); in npa_aq_enqueue_wait()
69 struct admin_queue *aq; in rvu_npa_aq_enq_inst() local
83 aq = block->aq; in rvu_npa_aq_enq_inst()
84 if (!aq) { in rvu_npa_aq_enq_inst()
101 inst.res_addr = (u64)aq->res->iova; in rvu_npa_aq_enq_inst()
106 spin_lock(&aq->lock); in rvu_npa_aq_enq_inst()
109 memset(aq->res->base, 0, aq->res->entry_sz); in rvu_npa_aq_enq_inst()
[all …]
/drivers/crypto/hisilicon/sec2/
Dsec_crypto.c1180 struct aead_request *aq = req->aead_req.aead_req; in GEN_SEC_AEAD_SETKEY_FUNC() local
1182 return sec_cipher_map(ctx, req, aq->src, aq->dst); in GEN_SEC_AEAD_SETKEY_FUNC()
1187 struct aead_request *aq = req->aead_req.aead_req; in sec_aead_sgl_unmap() local
1189 sec_cipher_unmap(ctx, req, aq->src, aq->dst); in sec_aead_sgl_unmap()
1492 struct aead_request *aq = a_req->aead_req; in sec_auth_bd_fill_xcm() local
1507 sec_sqe->type2.alen_ivllen = cpu_to_le32(aq->assoclen); in sec_auth_bd_fill_xcm()
1509 sec_sqe->type2.cipher_src_offset = cpu_to_le16((u16)aq->assoclen); in sec_auth_bd_fill_xcm()
1518 struct aead_request *aq = a_req->aead_req; in sec_auth_bd_fill_xcm_v3() local
1533 sqe3->a_len_key = cpu_to_le32(aq->assoclen); in sec_auth_bd_fill_xcm_v3()
1535 sqe3->cipher_src_offset = cpu_to_le16((u16)aq->assoclen); in sec_auth_bd_fill_xcm_v3()
[all …]

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