| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr_clk.c | 52 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk… in rv1_dump_clk_registers() argument
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
59 if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4) in rv1_dump_clk_registers()
60 bypass->dcfclk_bypass = 0; in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
70 if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4) in rv1_dump_clk_registers()
71 bypass->dispclk_pypass = 0; in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
76 if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4) in rv1_dump_clk_registers()
77 bypass->dprefclk_bypass = 0; in rv1_dump_clk_registers()
|
| /drivers/regulator/ |
| D | anatop-regulator.c | 30 bool bypass; member
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
100 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
113 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
115 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
117 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
126 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
130 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
270 sreg->bypass = true; in anatop_regulator_probe()
[all …]
|
| /drivers/clk/imx/ |
| D | clk-sscg-pll.c | 75 int bypass; member
146 temp_setup->bypass = PLL_BYPASS1; in clk_sscg_divq_lookup()
220 temp_setup->bypass = PLL_BYPASS_NONE; in clk_sscg_divf1_lookup()
280 setup->bypass = PLL_BYPASS2; in clk_sscg_pll_find_setup()
368 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); in clk_sscg_pll_set_rate()
405 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); in clk_sscg_pll_set_parent()
416 int bypass) in __clk_sscg_pll_determine_rate() argument
427 switch (bypass) { in __clk_sscg_pll_determine_rate()
443 rate, bypass); in __clk_sscg_pll_determine_rate()
|
| /drivers/md/bcache/ |
| D | stats.c | 183 bool hit, bool bypass) in mark_cache_stats() argument
185 if (!bypass) in mark_cache_stats()
198 bool hit, bool bypass) in bch_mark_cache_accounting() argument
202 mark_cache_stats(&dc->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
203 mark_cache_stats(&c->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
|
| D | request.c | 192 if (op->bypass) in bch_data_insert_start()
271 op->bypass = true; in bch_data_insert_start()
313 op->writeback, op->bypass); in bch_data_insert()
868 !s->cache_missed, s->iop.bypass); in cached_dev_read_done_bh()
869 trace_bcache_read(s->orig_bio, !s->cache_missed, s->iop.bypass); in cached_dev_read_done_bh()
889 if (s->cache_miss || s->iop.bypass) { in cached_dev_cache_miss()
984 s->iop.bypass = false; in cached_dev_write()
996 s->iop.bypass = true; in cached_dev_write()
1000 s->iop.bypass)) { in cached_dev_write()
1001 s->iop.bypass = false; in cached_dev_write()
[all …]
|
| D | request.h | 20 unsigned int bypass:1; member
|
| /drivers/clk/at91/ |
| D | sckc.c | 122 bool bypass, in at91_clk_register_slow_osc() argument
148 if (bypass) in at91_clk_register_slow_osc()
374 bool bypass; in at91sam9x5_sckc_register() local
394 bypass = of_property_read_bool(child, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
398 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_sckc_register()
405 xtal_name, 1200000, bypass, bits); in at91sam9x5_sckc_register()
468 bool bypass; in of_sam9x60_sckc_setup() local
484 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_sam9x60_sckc_setup()
486 xtal_name, 5000000, bypass, in of_sam9x60_sckc_setup()
|
| D | at91rm9200.c | 86 bool bypass; in at91rm9200_pmc_setup() local
109 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91rm9200_pmc_setup()
112 bypass); in at91rm9200_pmc_setup()
|
| D | at91sam9g45.c | 96 bool bypass; in at91sam9g45_pmc_setup() local
119 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9g45_pmc_setup()
122 bypass); in at91sam9g45_pmc_setup()
|
| D | at91sam9n12.c | 116 bool bypass; in at91sam9n12_pmc_setup() local
143 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9n12_pmc_setup()
146 bypass); in at91sam9n12_pmc_setup()
|
| D | sama5d3.c | 113 bool bypass; in sama5d3_pmc_setup() local
141 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in sama5d3_pmc_setup()
144 bypass); in sama5d3_pmc_setup()
|
| D | sama5d4.c | 128 bool bypass; in sama5d4_pmc_setup() local
156 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in sama5d4_pmc_setup()
159 bypass); in sama5d4_pmc_setup()
|
| D | at91sam9x5.c | 138 bool bypass; in at91sam9x5_pmc_setup() local
165 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam9x5_pmc_setup()
168 bypass); in at91sam9x5_pmc_setup()
|
| D | sama5d2.c | 154 bool bypass; in sama5d2_pmc_setup() local
183 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in sama5d2_pmc_setup()
186 bypass); in sama5d2_pmc_setup()
|
| D | at91sam9260.c | 340 bool bypass; in at91sam926x_pmc_setup() local
364 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in at91sam926x_pmc_setup()
367 bypass); in at91sam926x_pmc_setup()
|
| /drivers/clk/socfpga/ |
| D | clk-pll.c | 44 unsigned long bypass; in clk_pll_recalc_rate() local
47 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); in clk_pll_recalc_rate()
48 if (bypass & MAINPLL_BYPASS) in clk_pll_recalc_rate()
|
| /drivers/power/supply/ |
| D | bq25980_charger.c | 31 bool bypass; member
306 if (bq->state.bypass) in bq25980_set_input_curr_lim()
328 if (bq->state.bypass) { in bq25980_get_input_volt_lim()
350 if (bq->state.bypass) { in bq25980_set_input_volt_lim()
454 bq->state.bypass = en_bypass; in bq25980_set_bypass()
456 return bq->state.bypass; in bq25980_set_bypass()
604 state->bypass = chg_ctrl_2 & BQ25980_EN_BYPASS; in bq25980_get_state()
766 else if (state.bypass) in bq25980_get_charger_property()
768 else if (!state.bypass) in bq25980_get_charger_property()
828 old_state.bypass != new_state->bypass); in bq25980_state_changed()
[all …]
|
| /drivers/pwm/ |
| D | pwm-sun4i.c | 171 bool *bypass) in sun4i_pwm_calculate() argument
178 *bypass = sun4i_pwm->data->has_direct_mod_clk_output && in sun4i_pwm_calculate()
185 if (*bypass) in sun4i_pwm_calculate()
240 bool bypass; in sun4i_pwm_apply() local
253 &bypass); in sun4i_pwm_apply()
265 if (bypass) { in sun4i_pwm_apply()
|
| D | pwm-lpss.h | 28 bool bypass; member
|
| D | pwm-lpss.c | 139 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); in pwm_lpss_prepare_enable()
144 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true); in pwm_lpss_prepare_enable()
|
| /drivers/base/regmap/ |
| D | regcache.c | 349 bool bypass; in regcache_sync() local
359 bypass = map->cache_bypass; in regcache_sync()
393 map->cache_bypass = bypass; in regcache_sync()
445 bool bypass; in regcache_sync_region() local
455 bypass = map->cache_bypass; in regcache_sync_region()
474 map->cache_bypass = bypass; in regcache_sync_region()
|
| /drivers/gpu/drm/sun4i/ |
| D | sun4i_frontend.c | 411 u32 bypass; in sun4i_frontend_update_formats() local
465 bypass = 0; in sun4i_frontend_update_formats()
472 bypass = SUN4I_FRONTEND_BYPASS_CSC_EN; in sun4i_frontend_update_formats()
476 SUN4I_FRONTEND_BYPASS_CSC_EN, bypass); in sun4i_frontend_update_formats()
|
| /drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 882 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
1011 cdclk != dev_priv->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1117 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in skl_sanitize_cdclk()
1175 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1313 if (cdclk == dev_priv->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1430 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1432 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1434 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1437 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1582 cdclk != dev_priv->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
[all …]
|
| /drivers/staging/media/av7110/ |
| D | audio_function_calls.rst | 22 audio-set-bypass-mode
|
| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gt215.c | 371 u32 bypass; in prog_pll() local
375 bypass = nvkm_rd32(device, ctrl) & 0x00000008; in prog_pll()
376 if (!bypass) { in prog_pll()
|