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Searched refs:cdclk_state (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_cdclk.c2171 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) in intel_compute_min_cdclk() argument
2173 struct intel_atomic_state *state = cdclk_state->base.state; in intel_compute_min_cdclk()
2192 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2195 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2197 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2202 min_cdclk = cdclk_state->force_min_cdclk; in intel_compute_min_cdclk()
2204 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
2228 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) in bxt_compute_min_voltage_level() argument
2230 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_compute_min_voltage_level()
2246 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) in bxt_compute_min_voltage_level()
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Dintel_atomic_plane.c212 const struct intel_cdclk_state *cdclk_state; in intel_plane_calc_min_cdclk() local
237 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_plane_calc_min_cdclk()
238 if (IS_ERR(cdclk_state)) in intel_plane_calc_min_cdclk()
239 return PTR_ERR(cdclk_state); in intel_plane_calc_min_cdclk()
250 cdclk_state->min_cdclk[crtc->pipe]) in intel_plane_calc_min_cdclk()
258 cdclk_state->min_cdclk[crtc->pipe]); in intel_plane_calc_min_cdclk()
Dintel_bw.c649 struct intel_cdclk_state *cdclk_state; in intel_bw_calc_min_cdclk() local
651 cdclk_state = intel_atomic_get_new_cdclk_state(state); in intel_bw_calc_min_cdclk()
652 if (!cdclk_state) in intel_bw_calc_min_cdclk()
655 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_bw_calc_min_cdclk()
Dintel_audio.c943 struct intel_cdclk_state *cdclk_state; in glk_force_audio_cdclk_commit() local
951 cdclk_state = intel_atomic_get_cdclk_state(state); in glk_force_audio_cdclk_commit()
952 if (IS_ERR(cdclk_state)) in glk_force_audio_cdclk_commit()
953 return PTR_ERR(cdclk_state); in glk_force_audio_cdclk_commit()
955 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; in glk_force_audio_cdclk_commit()
Dintel_display.c3957 struct intel_cdclk_state *cdclk_state = in intel_crtc_disable_noatomic() local
4025 cdclk_state->min_cdclk[pipe] = 0; in intel_crtc_disable_noatomic()
4026 cdclk_state->min_voltage_level[pipe] = 0; in intel_crtc_disable_noatomic()
4027 cdclk_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic()
4160 const struct intel_cdclk_state *cdclk_state; in hsw_compute_ips_config() local
4162 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_compute_ips_config()
4163 if (IS_ERR(cdclk_state)) in hsw_compute_ips_config()
4164 return PTR_ERR(cdclk_state); in hsw_compute_ips_config()
4167 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_compute_ips_config()
7071 const struct intel_cdclk_state *cdclk_state) in hsw_ips_linetime_wm() argument
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