| /drivers/phy/ |
| D | phy-core-mipi-dphy.c | 23 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_get_default_config() argument
28 if (!cfg) in phy_mipi_dphy_get_default_config()
37 cfg->clk_miss = 0; in phy_mipi_dphy_get_default_config()
38 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_get_default_config()
39 cfg->clk_pre = 8; in phy_mipi_dphy_get_default_config()
40 cfg->clk_prepare = 38000; in phy_mipi_dphy_get_default_config()
41 cfg->clk_settle = 95000; in phy_mipi_dphy_get_default_config()
42 cfg->clk_term_en = 0; in phy_mipi_dphy_get_default_config()
43 cfg->clk_trail = 60000; in phy_mipi_dphy_get_default_config()
44 cfg->clk_zero = 262000; in phy_mipi_dphy_get_default_config()
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| /drivers/media/platform/exynos-gsc/ |
| D | gsc-regs.c | 22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
38 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
40 cfg |= GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
42 cfg &= ~GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
43 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
48 u32 cfg; in gsc_hw_set_gsc_irq_enable() local
50 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
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| /drivers/media/platform/exynos4-is/ |
| D | fimc-reg.c | 21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
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| D | fimc-lite-reg.c | 23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
31 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) in flite_hw_reset()
36 cfg |= FLITE_REG_CIGCTRL_SWRST; in flite_hw_reset()
37 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() local
43 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; in flite_hw_clear_pending_irq()
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| /drivers/media/platform/s3c-camif/ |
| D | camif-regs.c | 18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
28 cfg |= CIGCTRL_IRQ_LEVEL; in camif_hw_reset()
29 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_reset()
32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
33 cfg &= ~CIGCTRL_SWRST; in camif_hw_reset()
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| /drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_config.h | 121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val argument
131 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) argument
132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) argument
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| /drivers/pci/ |
| D | ecam.c | 32 struct pci_config_window *cfg; in pci_ecam_create() local
40 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in pci_ecam_create()
41 if (!cfg) in pci_ecam_create()
48 cfg->parent = dev; in pci_ecam_create()
49 cfg->ops = ops; in pci_ecam_create()
50 cfg->busr.start = busr->start; in pci_ecam_create()
51 cfg->busr.end = busr->end; in pci_ecam_create()
52 cfg->busr.flags = IORESOURCE_BUS; in pci_ecam_create()
53 cfg->bus_shift = bus_shift; in pci_ecam_create()
54 bus_range = resource_size(&cfg->busr); in pci_ecam_create()
[all …]
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| /drivers/net/ethernet/marvell/octeontx2/af/ |
| D | rpm.c | 63 u64 cfg, last; in rpm_lmac_tx_enable() local
68 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
69 last = cfg; in rpm_lmac_tx_enable()
71 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
73 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
75 if (cfg != last) in rpm_lmac_tx_enable()
76 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
83 u64 cfg; in rpm_lmac_rx_tx_enable() local
88 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_rx_tx_enable()
90 cfg |= RPM_RX_EN | RPM_TX_EN; in rpm_lmac_rx_tx_enable()
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| D | cgx.c | 200 u64 cfg; in cgx_lmac_get_p2x() local
202 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); in cgx_lmac_get_p2x()
204 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; in cgx_lmac_get_p2x()
234 static void cfg2mac(u64 cfg, u8 *mac_addr) in cfg2mac() argument
239 mac_addr[i] = (cfg >> (8 * index)) & 0xFF; in cfg2mac()
248 u64 cfg; in cgx_lmac_addr_set() local
256 cfg = mac2u64 (mac_addr); in cgx_lmac_addr_set()
263 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); in cgx_lmac_addr_set()
265 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); in cgx_lmac_addr_set()
266 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE | in cgx_lmac_addr_set()
[all …]
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_gsc.c | 65 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) argument
380 u32 cfg; in gsc_sw_reset() local
384 cfg = (GSC_SW_RESET_SRESET); in gsc_sw_reset()
385 gsc_write(cfg, GSC_SW_RESET); in gsc_sw_reset()
389 cfg = gsc_read(GSC_SW_RESET); in gsc_sw_reset()
390 if (!cfg) in gsc_sw_reset()
395 if (cfg) { in gsc_sw_reset()
401 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
402 cfg |= (GSC_IN_BASE_ADDR_MASK | in gsc_sw_reset()
404 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
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| D | exynos_drm_fimc.c | 139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
166 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
167 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | in fimc_set_type_ctrl()
174 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | in fimc_set_type_ctrl()
179 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
184 u32 cfg; in fimc_handle_jpeg() local
188 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_handle_jpeg()
[all …]
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| /drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 219 struct hdmi_8996_phy_pll_reg_cfg *cfg) in pll_calculate() argument
286 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
288 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
290 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
291 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
292 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
293 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
294 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
295 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
296 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
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| /drivers/scsi/cxlflash/ |
| D | main.c | 45 struct cxlflash_cfg *cfg = afu->parent; in process_cmd_err() local
46 struct device *dev = &cfg->dev->dev; in process_cmd_err()
157 struct cxlflash_cfg *cfg = afu->parent; in cmd_complete() local
158 struct device *dev = &cfg->dev->dev; in cmd_complete()
176 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in cmd_complete()
177 cfg->tmf_active = false; in cmd_complete()
178 wake_up_all_locked(&cfg->tmf_waitq); in cmd_complete()
179 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); in cmd_complete()
193 struct cxlflash_cfg *cfg = hwq->afu->parent; in flush_pending_cmds() local
213 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in flush_pending_cmds()
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| /drivers/net/wireless/microchip/wilc1000/ |
| D | wlan_cfg.c | 140 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
148 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
151 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
152 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
158 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
161 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
162 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
168 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
171 if (cfg->w[i].id == wid) in wilc_wlan_parse_response_frame()
172 cfg->w[i].val = get_unaligned_le32(&info[4]); in wilc_wlan_parse_response_frame()
[all …]
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| /drivers/phy/freescale/ |
| D | phy-fsl-imx8-mipi-dphy.c | 96 struct mixel_dphy_cfg cfg; member
156 struct mixel_dphy_cfg *cfg) in mixel_dphy_config_from_opts() argument
191 cfg->cn = denominator >> i; in mixel_dphy_config_from_opts()
192 cfg->co = 1 << i; in mixel_dphy_config_from_opts()
193 cfg->cm = numerator; in mixel_dphy_config_from_opts()
195 if (cfg->cm < 16 || cfg->cm > 255 || in mixel_dphy_config_from_opts()
196 cfg->cn < 1 || cfg->cn > 32 || in mixel_dphy_config_from_opts()
197 cfg->co < 1 || cfg->co > 8) { in mixel_dphy_config_from_opts()
199 cfg->cm, cfg->cn, cfg->co); in mixel_dphy_config_from_opts()
234 cfg->m_prg_hs_prepare = n; in mixel_dphy_config_from_opts()
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| /drivers/staging/media/atomisp/pci/runtime/isys/src/ |
| D | virtual_isys.c | 36 isp2401_input_system_cfg_t *cfg,
44 isp2401_input_system_cfg_t *cfg,
104 pixelgen_tpg_cfg_t *cfg);
110 pixelgen_prbs_cfg_t *cfg);
114 csi_rx_frontend_cfg_t *cfg);
120 csi_rx_backend_cfg_t *cfg);
125 stream2mmio_cfg_t *cfg);
131 ibuf_ctrl_cfg_t *cfg);
136 isys2401_dma_cfg_t *cfg);
142 isys2401_dma_port_cfg_t *cfg);
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| /drivers/net/ethernet/cavium/thunder/ |
| D | thunder_xcv.c | 67 u64 cfg; in xcv_init_hw() local
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
71 cfg &= ~DLL_RESET; in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
76 cfg &= ~CLK_RESET; in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
85 cfg &= ~0xFF03; in xcv_init_hw()
86 cfg |= CLKRX_BYP; in xcv_init_hw()
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| /drivers/iommu/ |
| D | io-pgtable-arm.c | 198 struct io_pgtable_cfg *cfg) in __arm_lpae_alloc_pages() argument
200 struct device *dev = cfg->iommu_dev; in __arm_lpae_alloc_pages()
213 if (!cfg->coherent_walk) { in __arm_lpae_alloc_pages()
237 struct io_pgtable_cfg *cfg) in __arm_lpae_free_pages() argument
239 if (!cfg->coherent_walk) in __arm_lpae_free_pages()
240 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), in __arm_lpae_free_pages()
246 struct io_pgtable_cfg *cfg) in __arm_lpae_sync_pte() argument
248 dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep), in __arm_lpae_sync_pte()
252 static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg) in __arm_lpae_clear_pte() argument
257 if (!cfg->coherent_walk) in __arm_lpae_clear_pte()
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| D | io-pgtable-arm-v7s.c | 51 #define _ARM_V7S_LVL_BITS(lvl, cfg) ((lvl) == 1 ? ((cfg)->ias - 20) : 8) argument
55 #define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl, cfg)) argument
56 #define ARM_V7S_TABLE_SIZE(lvl, cfg) \ argument
57 (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
62 #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1) argument
63 #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({ \ argument
65 ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
179 static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg) in arm_v7s_is_mtk_enabled() argument
182 (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT); in arm_v7s_is_mtk_enabled()
197 struct io_pgtable_cfg *cfg) in paddr_to_iopte() argument
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| /drivers/block/rsxx/ |
| D | config.c | 18 static void initialize_config(struct rsxx_card_cfg *cfg) in initialize_config() argument
20 cfg->hdr.version = RSXX_CFG_VERSION; in initialize_config()
22 cfg->data.block_size = RSXX_HW_BLK_SIZE; in initialize_config()
23 cfg->data.stripe_size = RSXX_HW_BLK_SIZE; in initialize_config()
24 cfg->data.vendor_id = RSXX_VENDOR_ID_IBM; in initialize_config()
25 cfg->data.cache_order = (-1); in initialize_config()
26 cfg->data.intr_coal.mode = RSXX_INTR_COAL_DISABLED; in initialize_config()
27 cfg->data.intr_coal.count = 0; in initialize_config()
28 cfg->data.intr_coal.latency = 0; in initialize_config()
31 static u32 config_data_crc32(struct rsxx_card_cfg *cfg) in config_data_crc32() argument
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| /drivers/leds/ |
| D | leds-lp55xx-common.c | 44 struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_reset_device() local
45 u8 addr = cfg->reset.addr; in lp55xx_reset_device()
46 u8 val = cfg->reset.val; in lp55xx_reset_device()
54 struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_detect_device() local
55 u8 addr = cfg->enable.addr; in lp55xx_detect_device()
56 u8 val = cfg->enable.val; in lp55xx_detect_device()
69 if (val != cfg->enable.val) in lp55xx_detect_device()
77 struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_post_init_device() local
79 if (!cfg->post_init_device) in lp55xx_post_init_device()
82 return cfg->post_init_device(chip); in lp55xx_post_init_device()
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| /drivers/media/platform/davinci/ |
| D | vpbe.c | 53 struct vpbe_config *cfg = vpbe_dev->cfg; in vpbe_current_encoder_info() local
56 return ((index == 0) ? &cfg->venc : in vpbe_current_encoder_info()
57 &cfg->ext_encoders[index-1]); in vpbe_current_encoder_info()
68 static int vpbe_find_encoder_sd_index(struct vpbe_config *cfg, in vpbe_find_encoder_sd_index() argument
71 char *encoder_name = cfg->outputs[index].subdev_name; in vpbe_find_encoder_sd_index()
75 if (!strcmp(encoder_name, cfg->venc.module_name)) in vpbe_find_encoder_sd_index()
78 for (i = 0; i < cfg->num_ext_encoders; i++) { in vpbe_find_encoder_sd_index()
80 cfg->ext_encoders[i].module_name)) in vpbe_find_encoder_sd_index()
98 struct vpbe_config *cfg = vpbe_dev->cfg; in vpbe_enum_outputs() local
101 if (temp_index >= cfg->num_outputs) in vpbe_enum_outputs()
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| /drivers/usb/serial/ |
| D | kl5kusb105.c | 109 struct klsi_105_port_settings cfg; member
219 priv->cfg.pktlen = 5; in klsi_105_port_probe()
220 priv->cfg.baudrate = kl5kusb105a_sio_b9600; in klsi_105_port_probe()
221 priv->cfg.databits = kl5kusb105a_dtb_8; in klsi_105_port_probe()
222 priv->cfg.unknown1 = 0; in klsi_105_port_probe()
223 priv->cfg.unknown2 = 1; in klsi_105_port_probe()
248 struct klsi_105_port_settings *cfg; in klsi_105_open() local
258 cfg = kmalloc(sizeof(*cfg), GFP_KERNEL); in klsi_105_open()
259 if (!cfg) in klsi_105_open()
262 cfg->pktlen = 5; in klsi_105_open()
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| /drivers/pinctrl/renesas/ |
| D | sh_pfc.h | 461 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
462 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
465 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
466 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
467 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
470 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
471 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
472 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
473 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
476 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ argument
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| /drivers/cpufreq/ |
| D | s3c24xx-cpufreq-debugfs.c | 38 struct s3c_cpufreq_config *cfg; in board_show() local
41 cfg = s3c_cpufreq_getconfig(); in board_show()
42 if (!cfg) { in board_show()
47 brd = cfg->board; in board_show()
67 struct s3c_cpufreq_config *cfg; in info_show() local
69 cfg = s3c_cpufreq_getconfig(); in info_show()
70 if (!cfg) { in info_show()
75 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); in info_show()
77 cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); in info_show()
78 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); in info_show()
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