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Searched refs:cfg0 (Results 1 – 16 of 16) sorted by relevance

/drivers/edac/
Docteon_edac-lmc.c40 union cvmx_lmcx_mem_cfg0 cfg0; in octeon_lmc_edac_poll() local
44 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx)); in octeon_lmc_edac_poll()
45 if (cfg0.s.sec_err || cfg0.s.ded_err) { in octeon_lmc_edac_poll()
54 if (cfg0.s.sec_err) { in octeon_lmc_edac_poll()
57 cfg0.s.sec_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
61 if (cfg0.s.ded_err) { in octeon_lmc_edac_poll()
64 cfg0.s.ded_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
68 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64); in octeon_lmc_edac_poll()
238 union cvmx_lmcx_mem_cfg0 cfg0; in octeon_lmc_edac_probe() local
240 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0)); in octeon_lmc_edac_probe()
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/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv10.c31 u32 cfg0 = nvkm_rd32(device, 0x100200); in nv10_ram_new() local
34 if (cfg0 & 0x00000001) in nv10_ram_new()
/drivers/net/wireless/mediatek/mt76/mt76x2/
Dphy.c187 u32 cfg0, cfg1; in mt76x2_configure_tx_delay() local
190 cfg0 = bw ? 0x000b0c01 : 0x00101101; in mt76x2_configure_tx_delay()
193 cfg0 = bw ? 0x000b0b01 : 0x00101001; in mt76x2_configure_tx_delay()
196 mt76_wr(dev, MT_TX_SW_CFG0, cfg0); in mt76x2_configure_tx_delay()
/drivers/gpu/drm/exynos/
Dexynos_drm_fimc.c1011 u32 cfg0, cfg1; in fimc_start() local
1023 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL); in fimc_start()
1024 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; in fimc_start()
1025 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; in fimc_start()
1026 fimc_write(ctx, cfg0, EXYNOS_MSCTRL); in fimc_start()
1031 cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT); in fimc_start()
1032 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; in fimc_start()
1033 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; in fimc_start()
1044 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; in fimc_start()
1045 fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT); in fimc_start()
/drivers/net/phy/
Ddp83640.c116 int cfg0; member
553 u16 cfg0 = 0, ver; in enable_status_frames() local
556 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; in enable_status_frames()
562 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); in enable_status_frames()
637 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; in recalibrate() local
654 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); in recalibrate()
659 cfg0 = ext_read(master, PAGE5, PSF_CFG0); in recalibrate()
735 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); in recalibrate()
737 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); in recalibrate()
/drivers/soc/qcom/
Dqcom-geni-se.c442 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; in geni_se_config_packing() local
470 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); in geni_se_config_packing()
474 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
478 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
/drivers/mtd/nand/raw/
Dqcom_nandc.c309 __le32 cfg0; member
462 u32 cfg0, cfg1; member
634 return &regs->cfg0; in offset_to_nandc_reg()
735 u32 cmd, cfg0, cfg1, ecc_bch_cfg; in update_rw_regs() local
748 cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
754 cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
762 nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0); in update_rw_regs()
2675 host->cfg0 = (cwperpage - 1) << CW_PER_PAGE in qcom_nand_attach_chip()
2724 host->cfg0, host->cfg1, host->ecc_buf_cfg, host->ecc_bch_cfg, in qcom_nand_attach_chip()
/drivers/pci/controller/
Dpcie-altera.c325 u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0; in get_tlp_header() local
330 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1; in get_tlp_header()
332 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1; in get_tlp_header()
/drivers/gpu/drm/i915/display/
Dintel_dsi_vbt.c289 u16 cfg0, cfg1; in chv_exec_gpio() local
328 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); in chv_exec_gpio()
333 vlv_iosf_sb_write(dev_priv, port, cfg0, in chv_exec_gpio()
/drivers/pinctrl/intel/
Dpinctrl-intel.c300 u32 cfg0, cfg1, mode; in intel_pin_dbg_show() local
309 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); in intel_pin_dbg_show()
312 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; in intel_pin_dbg_show()
318 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); in intel_pin_dbg_show()
/drivers/net/wireless/ath/ath11k/
Ddebugfs_htt_stats.c4377 cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_HWQS; in ath11k_prep_htt_stats_cfg_params()
4380 cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_TXQS; in ath11k_prep_htt_stats_cfg_params()
4383 cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_CMDQS; in ath11k_prep_htt_stats_cfg_params()
4386 cfg_params->cfg0 = HTT_STAT_PEER_INFO_MAC_ADDR; in ath11k_prep_htt_stats_cfg_params()
4387 cfg_params->cfg0 |= FIELD_PREP(GENMASK(15, 1), in ath11k_prep_htt_stats_cfg_params()
4399 cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_RINGS; in ath11k_prep_htt_stats_cfg_params()
4402 cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS; in ath11k_prep_htt_stats_cfg_params()
4405 cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE; in ath11k_prep_htt_stats_cfg_params()
4408 cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS; in ath11k_prep_htt_stats_cfg_params()
4573 cfg_params.cfg0 = HTT_STAT_DEFAULT_RESET_START_OFFSET; in ath11k_write_htt_stats_reset()
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Ddebugfs_sta.c784 cfg_params.cfg0 = HTT_STAT_PEER_INFO_MAC_ADDR; in ath11k_write_htt_peer_stats_reset()
785 cfg_params.cfg0 |= FIELD_PREP(GENMASK(15, 1), in ath11k_write_htt_peer_stats_reset()
Ddp.h1505 u32 cfg0; member
Ddp_tx.c1004 cmd->cfg_param0 = cfg_params->cfg0; in ath11k_dp_tx_htt_h2t_ext_stats_req()
/drivers/scsi/
Ddc395x.c180 u8 cfg0; /* Target configuration byte 0 */ member
667 eeprom->target[id].cfg0 = in eeprom_override()
1134 dcb->dev_mode = eeprom->target[dcb->target_id].cfg0; in reset_dev_param()
3567 dcb->dev_mode = eeprom->target[target].cfg0; in device_alloc()
4068 eeprom->target[0].cfg0); in print_eeprom_settings()
/drivers/pci/switch/
Dswitchtec.c642 set_fw_info_part(info, &fi->cfg0); in flash_part_info_gen3()
744 set_fw_info_part(info, &fi->cfg0); in flash_part_info_gen4()