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Searched refs:cfg_mask (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/armada/
Darmada_plane.c145 u32 cfg, cfg_mask, val; in armada_drm_primary_plane_atomic_update() local
200 cfg_mask = CFG_GRAFORMAT | in armada_drm_primary_plane_atomic_update()
207 cfg_mask = CFG_GRA_ENA; in armada_drm_primary_plane_atomic_update()
209 cfg = cfg_mask = 0; in armada_drm_primary_plane_atomic_update()
213 cfg_mask |= CFG_GRA_HSMOOTH; in armada_drm_primary_plane_atomic_update()
219 if (cfg_mask) in armada_drm_primary_plane_atomic_update()
220 armada_reg_queue_mod(regs, idx, cfg, cfg_mask, in armada_drm_primary_plane_atomic_update()
Darmada_overlay.c80 u32 cfg, cfg_mask, val; in armada_drm_overlay_plane_atomic_update() local
155 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT | in armada_drm_overlay_plane_atomic_update()
162 cfg_mask = CFG_DMA_ENA; in armada_drm_overlay_plane_atomic_update()
164 cfg = cfg_mask = 0; in armada_drm_overlay_plane_atomic_update()
168 cfg_mask |= CFG_DMA_HSMOOTH; in armada_drm_overlay_plane_atomic_update()
174 if (cfg_mask) in armada_drm_overlay_plane_atomic_update()
175 armada_reg_queue_mod(regs, idx, cfg, cfg_mask, in armada_drm_overlay_plane_atomic_update()
/drivers/pinctrl/bcm/
Dpinctrl-bcm281xx.c1338 u32 cfg_val, cfg_mask; in bcm281xx_pinctrl_pin_config_set() local
1342 cfg_mask = 0; in bcm281xx_pinctrl_pin_config_set()
1349 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1354 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1359 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1374 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask); in bcm281xx_pinctrl_pin_config_set()
1376 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); in bcm281xx_pinctrl_pin_config_set()
/drivers/net/wireless/realtek/rtw88/
Dmain.c984 u64 cfg_mask = GENMASK_ULL(63, 0); in rtw_update_rate_mask() local
1009 cfg_mask = mask->control[band].legacy; in rtw_update_rate_mask()
1012 cfg_mask = u64_encode_bits(mask->control[band].legacy, in rtw_update_rate_mask()
1018 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], in rtw_update_rate_mask()
1021 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], in rtw_update_rate_mask()
1025 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], in rtw_update_rate_mask()
1028 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], in rtw_update_rate_mask()
1032 ra_mask &= cfg_mask; in rtw_update_rate_mask()
/drivers/net/ethernet/qlogic/qed/
Dqed_init_fw_funcs.c1196 u32 reg_val, cfg_mask; in qed_set_vxlan_no_l2_enable() local
1202 cfg_mask = BIT(PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET); in qed_set_vxlan_no_l2_enable()
1206 reg_val |= cfg_mask; in qed_set_vxlan_no_l2_enable()
1215 reg_val &= ~cfg_mask; in qed_set_vxlan_no_l2_enable()
/drivers/net/ethernet/intel/ice/
Dice_common.c3153 u8 caps_mask, cfg_mask; in ice_phy_caps_equals_cfg() local
3163 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; in ice_phy_caps_equals_cfg()
3167 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || in ice_phy_caps_equals_cfg()