| /drivers/gpio/ |
| D | gpio-davinci.c | 194 struct davinci_gpio_controller *chips; in davinci_gpio_probe() local
230 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); in davinci_gpio_probe()
231 if (!chips) in davinci_gpio_probe()
239 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
240 if (chips->irqs[i] < 0) in davinci_gpio_probe()
241 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n"); in davinci_gpio_probe()
244 chips->chip.label = dev_name(dev); in davinci_gpio_probe()
246 chips->chip.direction_input = davinci_direction_in; in davinci_gpio_probe()
247 chips->chip.get = davinci_gpio_get; in davinci_gpio_probe()
248 chips->chip.direction_output = davinci_direction_out; in davinci_gpio_probe()
[all …]
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| /drivers/mtd/chips/ |
| D | Kconfig | 6 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
27 Intel chips.
37 chips, or if you wish to reduce the size of the kernel by including
38 support for only specific arrangements of flash chips, say 'Y'. This
50 data bits when writing the 'magic' commands to the chips. Saying
52 enabled, means that the CPU will not do any swapping; the chips
[all …]
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| D | cfi_cmdset_0002.c | 732 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp; in cfi_cmdset_0002()
733 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp; in cfi_cmdset_0002()
734 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp; in cfi_cmdset_0002()
743 cfi->chips[i].buffer_write_time_max = in cfi_cmdset_0002()
747 cfi->chips[i].buffer_write_time_max = 0; in cfi_cmdset_0002()
749 cfi->chips[i].buffer_write_time_max = in cfi_cmdset_0002()
750 max(cfi->chips[i].buffer_write_time_max, 2000); in cfi_cmdset_0002()
752 cfi->chips[i].ref_point_counter = 0; in cfi_cmdset_0002()
753 init_waitqueue_head(&(cfi->chips[i].wq)); in cfi_cmdset_0002()
1259 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); in cfi_amdstd_read()
[all …]
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| D | cfi_cmdset_0001.c | 564 cfi->chips[i].word_write_time = in cfi_cmdset_0001()
567 cfi->chips[i].word_write_time = 50000; in cfi_cmdset_0001()
570 cfi->chips[i].buffer_write_time = in cfi_cmdset_0001()
575 cfi->chips[i].erase_time = in cfi_cmdset_0001()
578 cfi->chips[i].erase_time = 2000000; in cfi_cmdset_0001()
582 cfi->chips[i].word_write_time_max = in cfi_cmdset_0001()
586 cfi->chips[i].word_write_time_max = 50000 * 8; in cfi_cmdset_0001()
590 cfi->chips[i].buffer_write_time_max = in cfi_cmdset_0001()
596 cfi->chips[i].erase_time_max = in cfi_cmdset_0001()
600 cfi->chips[i].erase_time_max = 2000000 * 8; in cfi_cmdset_0001()
[all …]
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| D | cfi_cmdset_0020.c | 155 cfi->chips[i].word_write_time = 128; in cfi_cmdset_0020()
156 cfi->chips[i].buffer_write_time = 128; in cfi_cmdset_0020()
157 cfi->chips[i].erase_time = 1024; in cfi_cmdset_0020()
158 cfi->chips[i].ref_point_counter = 0; in cfi_cmdset_0020()
159 init_waitqueue_head(&(cfi->chips[i].wq)); in cfi_cmdset_0020()
406 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); in cfi_staa_read()
633 ret = do_write_buffer(map, &cfi->chips[chipnum], in cfi_staa_write_buffers()
949 ret = do_erase_oneblock(map, &cfi->chips[chipnum], adr); in cfi_staa_erase_varsize()
982 chip = &cfi->chips[i]; in cfi_staa_sync()
1019 chip = &cfi->chips[i]; in cfi_staa_sync()
[all …]
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| /drivers/net/wireless/ralink/rt2x00/ |
| D | Kconfig | 29 Supported chips: RT2460.
41 Supported chips: RT2560.
56 Supported chips: RT2561, RT2561S & RT2661.
73 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890, RT3052,
86 Supported chips: RT3390
94 Supported chips: RT3060, RT3062, RT3562, RT3592
103 Supported chips: RT5390
111 Supported chips: RT3290
121 Supported chips: RT2571 & RT2572.
134 Supported chips: RT2571W, RT2573 & RT2671.
[all …]
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| /drivers/i2c/muxes/ |
| D | i2c-mux-pca954x.c | 94 static const struct chip_desc chips[] = { variable
197 { .compatible = "nxp,pca9540", .data = &chips[pca_9540] },
198 { .compatible = "nxp,pca9542", .data = &chips[pca_9542] },
199 { .compatible = "nxp,pca9543", .data = &chips[pca_9543] },
200 { .compatible = "nxp,pca9544", .data = &chips[pca_9544] },
201 { .compatible = "nxp,pca9545", .data = &chips[pca_9545] },
202 { .compatible = "nxp,pca9546", .data = &chips[pca_9546] },
203 { .compatible = "nxp,pca9547", .data = &chips[pca_9547] },
204 { .compatible = "nxp,pca9548", .data = &chips[pca_9548] },
205 { .compatible = "nxp,pca9846", .data = &chips[pca_9846] },
[all …]
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| D | i2c-mux-ltc4306.c | 53 static const struct chip_desc chips[] = { variable
202 { .compatible = "lltc,ltc4305", .data = &chips[ltc_4305] },
203 { .compatible = "lltc,ltc4306", .data = &chips[ltc_4306] },
222 chip = &chips[i2c_match_id(ltc4306_id, client)->driver_data]; in ltc4306_probe()
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| /drivers/mtd/lpddr/ |
| D | Kconfig | 6 tristate "Support for LPDDR flash chips"
10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
15 tristate "Detect flash chips by QINFO probe"
17 Device Information for LPDDR chips is offered through the Overlay
25 tristate "Support for LPDDR2-NVM flash chips"
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| D | lpddr_cmds.c | 75 chip = &lpddr->chips[0]; in lpddr_cmdset()
81 *chip = lpddr->chips[i]; in lpddr_cmdset()
489 struct flchip *chip = &lpddr->chips[chipnum]; in do_erase_oneblock()
517 struct flchip *chip = &lpddr->chips[chipnum]; in lpddr_read()
542 struct flchip *chip = &lpddr->chips[chipnum]; in lpddr_point()
583 chip = &lpddr->chips[chipnum]; in lpddr_point()
602 chip = &lpddr->chips[chipnum]; in lpddr_unpoint()
674 ret = do_write_buffer(map, &lpddr->chips[chipnum], in lpddr_writev()
722 struct flchip *chip = &lpddr->chips[chipnum]; in do_xxlock()
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| /drivers/cpufreq/ |
| D | powernv-cpufreq.c | 141 } *chips; variable
988 chips[i].restore = true; in powernv_cpufreq_occ_msg()
989 schedule_work(&chips[i].throttle); in powernv_cpufreq_occ_msg()
996 if (chips[i].id == omsg.chip) in powernv_cpufreq_occ_msg()
1001 chips[i].throttle_reason = omsg.throttle_status; in powernv_cpufreq_occ_msg()
1002 chips[i].reason[omsg.throttle_status]++; in powernv_cpufreq_occ_msg()
1006 chips[i].restore = true; in powernv_cpufreq_occ_msg()
1008 schedule_work(&chips[i].throttle); in powernv_cpufreq_occ_msg()
1074 chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL); in init_chip_info()
1075 if (!chips) { in init_chip_info()
[all …]
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| /drivers/iio/potentiometer/ |
| D | Kconfig | 45 potentiometer chips.
56 chips.
67 chips.
78 digital potentiometer chips.
96 digital potentiometer chips.
110 digital potentiometer chips.
122 digital potentiometer chips.
134 digital potentiometer chips.
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| /drivers/mtd/maps/ |
| D | Kconfig | 7 bool "Support non-linear mappings of flash chips"
10 paged mappings of flash chips.
17 ROM driver code to communicate with chips which are mapped
19 the physical address and size of the flash chips on your
42 This is the physical memory location at which the flash chips
52 This is the total length of the mapping of the flash chips on
54 physical memory map between the chips, this could be larger
74 and RAM driver code to communicate with chips which are mapped
135 which user-programmable flash chips are connected on various
143 The SC520 CDP board has two banks of CFI-compliant chips and one
[all …]
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| /drivers/memory/tegra/ |
| D | Kconfig | 21 Tegra20 chips. The EMC controls the external DRAM on the board.
32 Tegra30 chips. The EMC controls the external DRAM on the board.
44 Tegra124 chips. The EMC controls the external DRAM on the board.
58 Tegra210 chips. The EMC controls the external DRAM on the board.
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| /drivers/hwmon/ |
| D | Kconfig | 95 AD7416, AD7417 and AD7418 temperature monitoring chips.
105 and ADM1023 sensor chips and clones: Maxim MAX1617 and MAX1617A,
117 and Philips NE1619 sensor chips.
149 and ADM1030 sensor chips.
159 sensor chips.
170 Dallas DS1780, National Semiconductor LM81 sensor chips.
189 ADT7310 and ADT7320 temperature monitoring chips.
200 ADT7410 and ADT7420 temperature monitoring chips.
220 ADT7462 temperature monitoring chips.
230 ADT7470 temperature monitoring chips.
[all …]
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| /drivers/mtd/nand/raw/ |
| D | oxnas_nand.c | 34 struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS]; member
147 oxnas->chips[oxnas->nchips++] = chip; in oxnas_nand_probe()
166 chip = oxnas->chips[i]; in oxnas_nand_probe()
183 chip = oxnas->chips[i]; in oxnas_nand_remove()
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| D | Kconfig | 124 The CS553x companion chips for the AMD Geode processor
170 chips) NAND controller. This is the default for the PHYTEC 3250
181 Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND
248 Various Freescale chips, including the 8313, include a NAND Flash
260 Various Freescale chips e.g P1010, include a NAND Flash machine
270 Enables support for NAND Flash chips wired onto Freescale PowerPC
306 Enable the driver for NAND flash chips on Texas Instruments
320 Enables support for NAND Flash chips wired onto Socrates board.
329 Enables support for NAND Flash chips on the ST Microelectronics
336 Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
[all …]
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| D | nand_bbt.c | 557 int i, chips; in search_bbt() local
574 chips = nanddev_ntargets(&this->base); in search_bbt()
578 chips = 1; in search_bbt()
582 for (i = 0; i < chips; i++) { in search_bbt()
610 for (i = 0; i < chips; i++) { in search_bbt()
953 int i, chips, writeops, create, chipsel, res, res2; in check_create() local
960 chips = nanddev_ntargets(&this->base); in check_create()
962 chips = 1; in check_create()
964 for (i = 0; i < chips; i++) { in check_create()
1134 int i, j, chips, block, nrblocks, update; in mark_bbt_region() local
[all …]
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| /drivers/nfc/st-nci/ |
| D | Kconfig | 5 STMicroelectronics NFC NCI chips core driver. It implements the chipset
15 STMicroelectronics NFC NCI chips family.
27 STMicroelectronics NFC NCI chips family.
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| /drivers/net/dsa/ |
| D | Kconfig | 17 switch chips.
42 Ethernet switch chips.
69 switch chips.
80 chips, currently only RTL8366RB.
88 switch chips.
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| /drivers/rtc/ |
| D | Kconfig | 170 88PM860x chips.
180 88PM80x chips.
211 clock chips.
242 chips.
253 chips (often with battery backup) connected with I2C. This driver
255 ST M41T00, EPSON RX-8025, Intersil ISL12057 and probably other chips.
259 The first seven registers on these chips hold an RTC, and other
285 DS1374 real-time clock chips. If an interrupt is associated
298 real-time clock chips.
400 Ricoh R2025S/D, RS5C372A, RS5C372B, RV5C386, and RV5C387A RTC chips.
[all …]
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| /drivers/pinctrl/ |
| D | pinctrl-mcp23s08_spi.c | 152 int chips; in mcp23s08_probe() local
178 chips = hweight_long(spi_present_mask); in mcp23s08_probe()
180 data = devm_kzalloc(dev, struct_size(data, chip, chips), GFP_KERNEL); in mcp23s08_probe()
187 data->mcp[addr] = &data->chip[--chips]; in mcp23s08_probe()
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| /drivers/gpu/drm/mgag200/ |
| D | Kconfig | 8 This is a KMS driver for Matrox G200 chips. It supports the original
9 MGA G200 desktop chips and the server variants. It requires 0.3.0
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| /drivers/hwmon/pmbus/ |
| D | ucd9200.c | 21 enum chips { ucd9200, ucd9220, ucd9222, ucd9224, ucd9240, ucd9244, ucd9246, enum
79 enum chips chip; in ucd9200_probe()
106 chip = (enum chips)of_device_get_match_data(&client->dev); in ucd9200_probe()
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| /drivers/net/wireless/atmel/ |
| D | Kconfig | 24 chips. This driver supports standard Linux wireless extensions.
48 Atmel at76c502 and at76c504 chips.
56 at76c505 or at76c505a chips.
|