Home
last modified time | relevance | path

Searched refs:clk_mgr_internal (Results 1 – 25 of 37) sorted by relevance

12

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr_smu_msg.h90 struct clk_mgr_internal;
92 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
93 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
94 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
95 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
96 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
97 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
98 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
99 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
100 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t…
[all …]
Ddcn30_clk_mgr_smu_msg.c52 static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn30_smu_wait_for_response()
74 static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32… in dcn30_smu_send_msg_with_param()
100 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) in dcn30_smu_test_message()
114 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) in dcn30_smu_get_smu_version()
130 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr) in dcn30_smu_check_driver_if_version()
149 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr) in dcn30_smu_check_msg_header_version()
167 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) in dcn30_smu_set_dram_addr_high()
175 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) in dcn30_smu_set_dram_addr_low()
183 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) in dcn30_smu_transfer_wm_table_smu_2_dram()
191 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) in dcn30_smu_transfer_wm_table_dram_2_smu()
[all …]
Ddcn30_clk_mgr.c86 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *ent… in dcn3_init_single_clock()
107 static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) in dcn3_build_wm_range_table()
162 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_init_clocks()
223 static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) in dcn30_get_vco_frequency_from_reg()
247 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_update_clocks()
363 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_notify_wm_ranges()
394 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_set_hard_min_memclk()
415 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_set_hard_max_memclk()
427 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_get_memclk_states_from_smu()
448 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_is_smu_present()
[all …]
Ddcn30_clk_mgr.h32 struct clk_mgr_internal *clk_mgr,
36 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr_vbios_smu.h29 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
30 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
31 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
32 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
33 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_d…
34 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
35 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
36 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
37 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
38 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
[all …]
Drn_clk_mgr_vbios_smu.c70 static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, u… in rn_smu_wait_for_response()
89 int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigne… in rn_vbios_smu_send_msg_with_param()
110 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_get_smu_version()
119 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rn_vbios_smu_set_dispclk()
146 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_set_dprefclk()
160 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in rn_vbios_smu_set_hard_min_dcfclk()
175 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_d… in rn_vbios_smu_set_min_deep_sleep_dcfclk()
190 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) in rn_vbios_smu_set_phyclk()
198 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in rn_vbios_smu_set_dppclk()
214 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state stat… in rn_vbios_smu_set_dcn_low_power_state()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Ddcn301_smu.h150 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
151 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
152 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
153 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
154 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
156 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
157 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
158 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
159 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
[all …]
Ddcn301_smu.c73 static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn301_smu_wait_for_response()
92 struct clk_mgr_internal *clk_mgr, in dcn301_smu_send_msg_with_param()
114 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn301_smu_get_smu_version()
126 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn301_smu_set_dispclk()
141 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn301_smu_set_dprefclk()
157 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn301_smu_set_hard_min_dcfclk()
171 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf… in dcn301_smu_set_min_deep_sleep_dcfclk()
185 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn301_smu_set_dppclk()
199 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn301_smu_set_display_idle_optimization()
211 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn301_smu_enable_phy_refclk_pwrdwn()
[all …]
Dvg_clk_mgr.h38 struct clk_mgr_internal base;
47 void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_smu.c80 static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn31_smu_wait_for_response()
99 struct clk_mgr_internal *clk_mgr, in dcn31_smu_send_msg_with_param()
140 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn31_smu_get_smu_version()
149 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn31_smu_set_dispclk()
165 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn31_smu_set_dprefclk()
182 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn31_smu_set_hard_min_dcfclk()
200 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc… in dcn31_smu_set_min_deep_sleep_dcfclk()
218 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) in dcn31_smu_set_dppclk()
233 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) in dcn31_smu_set_display_idle_optimization()
248 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) in dcn31_smu_enable_phy_refclk_pwrdwn()
[all …]
Ddcn31_smu.h254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
257 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
258 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfc…
259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
263 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
[all …]
Ddcn31_clk_mgr.h38 struct clk_mgr_internal base;
47 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
/drivers/gpu/drm/amd/display/dc/clk_mgr/
Dclk_mgr.c142 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
155 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
165 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
175 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
199 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
213 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
241 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create()
302 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c114 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz) in dce_adjust_dp_ref_freq_for_ss()
131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz()
157 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_get_dp_ref_freq_khz()
198 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_required_clocks_state()
233 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_set_clock()
272 static void dce_clock_read_integrated_info(struct clk_mgr_internal *clk_mgr_dce) in dce_clock_read_integrated_info()
325 void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce) in dce_clock_read_ss_info()
399 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_update_clocks()
436 struct clk_mgr_internal *clk_mgr) in dce_clk_mgr_construct()
Ddce_clk_mgr.h33 int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz);
44 struct clk_mgr_internal *clk_mgr_dce);
46 void dce_clock_read_ss_info(struct clk_mgr_internal *dccg_dce);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.h32 struct clk_mgr_internal *clk_mgr);
36 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz);
37 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr);
Ddce112_clk_mgr.c72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock()
126 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz) in dce112_set_dispclk()
169 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dce112_set_dprefclk()
199 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks()
229 struct clk_mgr_internal *clk_mgr) in dce112_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_vbios_smu.c84 static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, … in rv1_smu_wait_for_response()
102 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsign… in rv1_vbios_smu_send_msg_with_param()
123 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rv1_vbios_smu_set_dispclk()
146 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rv1_vbios_smu_set_dprefclk()
Drv1_clk_mgr_vbios_smu.h29 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
30 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
Drv1_clk_mgr.c42 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_c… in rv1_determine_dppclk_threshold()
89 struct clk_mgr_internal *clk_mgr, in ramp_up_dispclk_with_dpp()
194 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_update_clocks()
296 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_enable_pme_wa()
319 void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_… in rv1_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.h36 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
42 struct clk_mgr_internal *clk_mgr,
53 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c56 static void dce121_clock_patch_xgmi_ss_info(struct clk_mgr_internal *clk_mgr_dce) in dce121_clock_patch_xgmi_ss_info()
88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_update_clocks()
128 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce120_clk_mgr_construct()
140 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce121_clk_mgr_construct()
Ddce120_clk_mgr.h29 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);
30 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr);
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr_internal.h70 container_of(clk_mgr, struct clk_mgr_internal, base)
214 struct clk_mgr_internal { struct
292 int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); argument
293 int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
Ddce60_clk_mgr.c85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_get_dp_ref_freq_khz()
124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_update_clocks()
161 struct clk_mgr_internal *clk_mgr) in dce60_clk_mgr_construct()

12