Searched refs:clock_ctl (Results 1 – 3 of 3) sorted by relevance
/drivers/hid/ |
D | hid-ft260.c | 139 u8 clock_ctl; /* 0 - 12MHz, 1 - 24MHz, 2 - 48MHz */ member 170 u8 clock_ctl; /* 0 - 12MHz, 1 - 24MHz, 2 - 48MHz */ member 750 ft260_dbg("clock_ctl: 0x%02x\n", cfg.clock_ctl); in ft260_is_interface_enabled() 873 FT260_SSTAT_ATTR_SHOW(clock_ctl); 874 FT260_BYTE_ATTR_STORE(clock_ctl, ft260_set_system_clock_report, 876 static DEVICE_ATTR_RW(clock_ctl);
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/drivers/memstick/host/ |
D | jmb38x_ms.c | 679 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0; in jmb38x_ms_set_param() local 725 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param() 732 clock_ctl |= CLOCK_CONTROL_40MHZ; in jmb38x_ms_set_param() 738 clock_ctl |= CLOCK_CONTROL_50MHZ; in jmb38x_ms_set_param() 745 writel(clock_ctl, host->addr + CLOCK_CONTROL); in jmb38x_ms_set_param()
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/drivers/net/ethernet/broadcom/ |
D | tg3.c | 6146 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write() local 6148 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP); in tg3_refclk_write() 6151 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME); in tg3_refclk_write() 6267 u32 clock_ctl; in tg3_ptp_enable() local 6280 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable() 6281 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK; in tg3_ptp_enable() 6309 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0); in tg3_ptp_enable() 6312 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl); in tg3_ptp_enable()
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