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Searched refs:controller (Results 1 – 25 of 549) sorted by relevance

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/drivers/spi/
Dspi-qup.c156 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
172 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
174 return controller->n_words * controller->w_size; in spi_qup_len()
177 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
179 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
184 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
190 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
199 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
202 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
[all …]
Dspi-fsl-lpspi.c174 static bool fsl_lpspi_can_dma(struct spi_controller *controller, in fsl_lpspi_can_dma() argument
180 if (!controller->dma_rx) in fsl_lpspi_can_dma()
197 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) in lpspi_prepare_xfer_hardware() argument
200 spi_controller_get_devdata(controller); in lpspi_prepare_xfer_hardware()
212 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) in lpspi_unprepare_xfer_hardware() argument
215 spi_controller_get_devdata(controller); in lpspi_unprepare_xfer_hardware()
331 static int fsl_lpspi_dma_configure(struct spi_controller *controller) in fsl_lpspi_dma_configure() argument
337 spi_controller_get_devdata(controller); in fsl_lpspi_dma_configure()
357 ret = dmaengine_slave_config(controller->dma_tx, &tx); in fsl_lpspi_dma_configure()
368 ret = dmaengine_slave_config(controller->dma_rx, &rx); in fsl_lpspi_dma_configure()
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Dspi-pxa2xx-dma.c23 struct spi_message *msg = drv_data->controller->cur_msg; in pxa2xx_spi_dma_transfer_complete()
52 spi_finalize_current_transfer(drv_data->controller); in pxa2xx_spi_dma_transfer_complete()
67 spi_get_ctldata(drv_data->controller->cur_msg->spi); in pxa2xx_spi_dma_prepare_one()
95 chan = drv_data->controller->dma_tx; in pxa2xx_spi_dma_prepare_one()
102 chan = drv_data->controller->dma_rx; in pxa2xx_spi_dma_prepare_one()
123 dmaengine_terminate_async(drv_data->controller->dma_rx); in pxa2xx_spi_dma_transfer()
124 dmaengine_terminate_async(drv_data->controller->dma_tx); in pxa2xx_spi_dma_transfer()
162 dmaengine_terminate_async(drv_data->controller->dma_tx); in pxa2xx_spi_dma_prepare()
169 dma_async_issue_pending(drv_data->controller->dma_rx); in pxa2xx_spi_dma_start()
170 dma_async_issue_pending(drv_data->controller->dma_tx); in pxa2xx_spi_dma_start()
[all …]
DKconfig12 controller and a chipselect. Most SPI slaves don't support
16 eeprom and flash memory, codecs and various other controller
33 sysfs, and debugfs support in SPI controller and protocol drivers.
44 If your system has an master-capable SPI controller (which
46 controller and the protocol drivers for the SPI slave chips
79 Altera SPI master controller. The SPI master is connected
83 tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
86 This enables support for the SPI controller present on the
90 tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
94 This enables support for the SPI controller present on the
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Dspi-pxa2xx.c365 spi_controller_get_devdata(spi->controller); in lpss_ssp_select_cs()
388 (drv_data->controller->max_speed_hz / 2)); in lpss_ssp_select_cs()
395 spi_controller_get_devdata(spi->controller); in lpss_ssp_cs_control()
432 spi_controller_get_devdata(spi->controller); in cs_assert()
452 spi_controller_get_devdata(spi->controller); in cs_deassert()
600 if (drv_data->controller->cur_msg) { in reset_sccr1()
601 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); in reset_sccr1()
641 drv_data->controller->cur_msg->status = err; in int_error_stop()
642 spi_finalize_current_transfer(drv_data->controller); in int_error_stop()
649 spi_finalize_current_transfer(drv_data->controller); in int_transfer_complete()
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/drivers/usb/musb/
Dmusb_cppi41.c37 struct dma_controller controller; member
61 if (!is_host_active(cppi41_channel->controller->controller.musb)) in save_rx_toggle()
187 struct cppi41_dma_controller *controller; in cppi41_recheck_tx_req() local
193 controller = container_of(timer, struct cppi41_dma_controller, in cppi41_recheck_tx_req()
195 musb = controller->controller.musb; in cppi41_recheck_tx_req()
198 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list, in cppi41_recheck_tx_req()
210 if (!list_empty(&controller->early_tx_list) && in cppi41_recheck_tx_req()
211 !hrtimer_is_queued(&controller->early_tx)) { in cppi41_recheck_tx_req()
213 hrtimer_forward_now(&controller->early_tx, 20 * NSEC_PER_USEC); in cppi41_recheck_tx_req()
226 struct cppi41_dma_controller *controller; in cppi41_dma_callback() local
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Dmusbhsdma.c55 struct musb_dma_controller *controller; member
65 struct dma_controller controller; member
76 static void dma_controller_stop(struct musb_dma_controller *controller) in dma_controller_stop() argument
78 struct musb *musb = controller->private_data; in dma_controller_stop()
82 if (controller->used_channels != 0) { in dma_controller_stop()
83 dev_err(musb->controller, in dma_controller_stop()
87 if (controller->used_channels & (1 << bit)) { in dma_controller_stop()
88 channel = &controller->channel[bit].channel; in dma_controller_stop()
91 if (!controller->used_channels) in dma_controller_stop()
101 struct musb_dma_controller *controller = container_of(c, in dma_channel_allocate() local
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Dux500_dma.c32 struct ux500_dma_controller *controller; member
43 struct dma_controller controller; member
59 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", in ux500_dma_callback()
82 struct musb *musb = ux500_channel->controller->private_data; in ux500_configure_channel()
84 ux500_channel->controller->phy_base); in ux500_configure_channel()
86 dev_dbg(musb->controller, in ux500_configure_channel()
131 struct ux500_dma_controller *controller = container_of(c, in ux500_dma_channel_allocate() local
132 struct ux500_dma_controller, controller); in ux500_dma_channel_allocate()
134 struct musb *musb = controller->private_data; in ux500_dma_channel_allocate()
147 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : in ux500_dma_channel_allocate()
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Dcppi_dma.c119 c->controller = cppi; in cppi_pool_init()
138 struct cppi *cppi = c->controller; in cppi_pool_free()
143 c->controller = NULL; in cppi_pool_free()
155 static void cppi_controller_start(struct cppi *controller) in cppi_controller_start() argument
161 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { in cppi_controller_start()
162 controller->tx[i].transmit = true; in cppi_controller_start()
163 controller->tx[i].index = i; in cppi_controller_start()
165 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { in cppi_controller_start()
166 controller->rx[i].transmit = false; in cppi_controller_start()
167 controller->rx[i].index = i; in cppi_controller_start()
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Dtusb6010_omap.c51 struct dma_controller controller; member
66 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", in tusb_omap_use_shared_dmareq()
103 struct device *dev = musb->controller; in tusb_omap_dma_cb()
111 dev_dbg(musb->controller, "ep%i %s dma callback\n", in tusb_omap_dma_cb()
123 dev_dbg(musb->controller, "Corrupt %s XFR_SIZE: 0x%08lx\n", in tusb_omap_dma_cb()
131 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); in tusb_omap_dma_cb()
137 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); in tusb_omap_dma_cb()
169 dev_dbg(musb->controller, "terminating short tx packet\n"); in tusb_omap_dma_cb()
187 struct device *dev = musb->controller; in tusb_omap_dma_program()
226 dev_dbg(musb->controller, "Busy %s dma, not using: %08x\n", in tusb_omap_dma_program()
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/drivers/gpio/
Dgpio-zevio.c77 struct zevio_gpio *controller = gpiochip_get_data(chip); in zevio_gpio_get() local
80 spin_lock(&controller->lock); in zevio_gpio_get()
81 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); in zevio_gpio_get()
83 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); in zevio_gpio_get()
85 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_get()
86 spin_unlock(&controller->lock); in zevio_gpio_get()
93 struct zevio_gpio *controller = gpiochip_get_data(chip); in zevio_gpio_set() local
96 spin_lock(&controller->lock); in zevio_gpio_set()
97 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_set()
103 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); in zevio_gpio_set()
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/drivers/mtd/spi-nor/controllers/
Daspeed-smc.c94 struct aspeed_smc_controller *controller; member
197 #define SEGMENT_ADDR_REG(controller, cs) \ argument
198 ((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4)
258 return BIT(chip->controller->info->we0 + chip->cs); in aspeed_smc_chip_write_bit()
263 struct aspeed_smc_controller *controller = chip->controller; in aspeed_smc_chip_check_config() local
266 reg = readl(controller->regs + CONFIG_REG); in aspeed_smc_chip_check_config()
271 dev_dbg(controller->dev, "config write is not set ! @%p: 0x%08x\n", in aspeed_smc_chip_check_config()
272 controller->regs + CONFIG_REG, reg); in aspeed_smc_chip_check_config()
274 writel(reg, controller->regs + CONFIG_REG); in aspeed_smc_chip_check_config()
312 mutex_lock(&chip->controller->mutex); in aspeed_smc_prep()
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/drivers/pci/hotplug/
Dpciehp.h88 struct controller { struct
160 void pciehp_request(struct controller *ctrl, int action);
161 void pciehp_handle_button_press(struct controller *ctrl);
162 void pciehp_handle_disable_request(struct controller *ctrl);
163 void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
164 int pciehp_configure_device(struct controller *ctrl);
165 void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
167 struct controller *pcie_init(struct pcie_device *dev);
168 int pcie_init_notification(struct controller *ctrl);
169 void pcie_shutdown_notification(struct controller *ctrl);
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Dcpqphp.h261 struct controller *ctrl;
277 struct controller { struct
278 struct controller *next; argument
395 void cpqhp_create_debugfs_files(struct controller *ctrl);
396 void cpqhp_remove_debugfs_files(struct controller *ctrl);
401 int cpqhp_find_available_resources(struct controller *ctrl,
408 int cpqhp_process_SI(struct controller *ctrl, struct pci_func *func);
409 int cpqhp_process_SS(struct controller *ctrl, struct pci_func *func);
410 int cpqhp_hardware_test(struct controller *ctrl, int test_num);
417 int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num,
[all …]
Dcpci_hotplug_core.c48 static struct cpci_hp_controller *controller; variable
78 if (controller->ops->set_power) in enable_slot()
79 retval = controller->ops->set_power(slot, 1); in enable_slot()
112 if (controller->ops->set_power) { in disable_slot()
113 retval = controller->ops->set_power(slot, 0); in disable_slot()
134 if (controller->ops->get_power) in cpci_get_power_status()
135 power = controller->ops->get_power(slot); in cpci_get_power_status()
197 if (!(controller && bus)) in cpci_hp_register_bus()
275 if ((controller->irq_flags & IRQF_SHARED) && in cpci_hp_intr()
276 !controller->ops->check_irq(controller->dev_id)) { in cpci_hp_intr()
[all …]
Dpciehp_hpc.c48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) in ctrl_dev()
57 static inline int pciehp_request_irq(struct controller *ctrl) in pciehp_request_irq()
77 static inline void pciehp_free_irq(struct controller *ctrl) in pciehp_free_irq()
85 static int pcie_poll_cmd(struct controller *ctrl, int timeout) in pcie_poll_cmd()
111 static void pcie_wait_cmd(struct controller *ctrl) in pcie_wait_cmd()
156 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, in pcie_do_write_cmd()
212 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) in pcie_write_cmd()
218 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) in pcie_write_cmd_nowait()
234 int pciehp_check_link_active(struct controller *ctrl) in pciehp_check_link_active()
290 int pciehp_check_link_status(struct controller *ctrl) in pciehp_check_link_status()
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/drivers/pci/controller/dwc/
DKconfig23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
33 This controller can work either as EP or RC. In order to enable
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
48 This controller can work either as EP or RC. In order to enable
62 Enables support for the PCIe controller in the Designware IP to
63 work in host mode. There are two instances of PCIe controller in
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/drivers/char/agp/
Dfrontend.c293 struct agp_controller *controller; in agp_find_controller_by_pid() local
295 controller = agp_fe.controllers; in agp_find_controller_by_pid()
297 while (controller != NULL) { in agp_find_controller_by_pid()
298 if (controller->pid == id) in agp_find_controller_by_pid()
299 return controller; in agp_find_controller_by_pid()
300 controller = controller->next; in agp_find_controller_by_pid()
308 struct agp_controller *controller; in agp_create_controller() local
310 controller = kzalloc(sizeof(struct agp_controller), GFP_KERNEL); in agp_create_controller()
311 if (controller == NULL) in agp_create_controller()
314 controller->pid = id; in agp_create_controller()
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/drivers/mtd/nand/raw/
DKconfig19 tristate "Denali NAND controller on Intel Moorestown"
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
32 controller as a DT device.
35 tristate "Amstrad E3 NAND controller"
42 tristate "OMAP2, OMAP3, OMAP4 and Keystone NAND controller"
68 This enables the driver for the NAND flash controller on the
72 tristate "IBM/MCC 4xx NAND controller"
80 tristate "Samsung S3C NAND controller"
83 This enables the NAND flash controller on the S3C24xx and S3C64xx
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Dcs553x_nand.c99 to_cs553x(struct nand_controller *controller) in to_cs553x() argument
101 return container_of(controller, struct cs553x_nand_controller, base); in to_cs553x()
202 struct cs553x_nand_controller *cs553x = to_cs553x(this->controller); in cs553x_exec_op()
225 struct cs553x_nand_controller *cs553x = to_cs553x(this->controller); in cs_enable_hwecc()
233 struct cs553x_nand_controller *cs553x = to_cs553x(this->controller); in cs_calculate_ecc()
277 struct cs553x_nand_controller *controller; in cs553x_init_one() local
291 controller = kzalloc(sizeof(*controller), GFP_KERNEL); in cs553x_init_one()
292 if (!controller) { in cs553x_init_one()
297 this = &controller->chip; in cs553x_init_one()
298 nand_controller_init(&controller->base); in cs553x_init_one()
[all …]
/drivers/pci/controller/
DKconfig3 menu "PCI controller drivers"
7 bool "Marvell EBU PCIe controller"
15 tristate "Aardvark PCIe controller"
22 controller is part of the South Bridge of the Marvel Armada
31 NWL PCIe controller. The controller can act as Root Port
36 bool "Faraday Technology FTPCI100 PCI controller"
41 bool "Intel IXP4xx PCI controller"
46 Say Y here if you want support for the PCI host controller found
50 bool "NVIDIA Tegra PCIe controller"
54 Say Y here if you want support for the PCIe host controller found
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/drivers/usb/host/
Dohci-dbg.c101 ohci_dump_status (struct ohci_hcd *controller, char **next, unsigned *size) in ohci_dump_status() argument
103 struct ohci_regs __iomem *regs = controller->regs; in ohci_dump_status()
106 temp = ohci_readl (controller, &regs->revision) & 0xff; in ohci_dump_status()
107 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
111 rh_state_string(controller)); in ohci_dump_status()
113 temp = ohci_readl (controller, &regs->control); in ohci_dump_status()
114 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
128 temp = ohci_readl (controller, &regs->cmdstatus); in ohci_dump_status()
129 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
138 ohci_dump_intr_mask (controller, "intrstatus", in ohci_dump_status()
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/drivers/clk/samsung/
DKconfig4 bool "Samsung Exynos clock controller support" if COMPILE_TEST
16 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST
19 Support for the clock controller present on the Samsung S3C64xx SoCs.
23 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST
26 Support for the clock controller present on the Samsung S5Pv210 SoCs.
30 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST
33 Support for the clock controller present on the Samsung
37 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST
40 Support for the clock controller present on the Samsung
45 bool "Samsung Exynos5250 clock controller support" if COMPILE_TEST
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/drivers/mailbox/
Dbcm2835-mailbox.c58 struct mbox_controller controller; member
63 return container_of(link->mbox, struct bcm2835_mbox, controller); in bcm2835_link_mbox()
69 struct device *dev = mbox->controller.dev; in bcm2835_mbox_irq()
70 struct mbox_chan *link = &mbox->controller.chans[0]; in bcm2835_mbox_irq()
87 dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); in bcm2835_send_data()
163 mbox->controller.txdone_poll = true; in bcm2835_mbox_probe()
164 mbox->controller.txpoll_period = 5; in bcm2835_mbox_probe()
165 mbox->controller.ops = &bcm2835_mbox_chan_ops; in bcm2835_mbox_probe()
166 mbox->controller.of_xlate = &bcm2835_mbox_index_xlate; in bcm2835_mbox_probe()
167 mbox->controller.dev = dev; in bcm2835_mbox_probe()
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/drivers/clk/rockchip/
DKconfig5 bool "Rockchip clock controller common support"
9 Say y here to enable common clock controller for Rockchip platforms.
13 bool "Rockchip PX30 clock controller support"
20 bool "Rockchip RV110x clock controller support"
27 bool "Rockchip RK3036 clock controller support"
34 bool "Rockchip RK312x clock controller support"
41 bool "Rockchip RK3188 clock controller support"
48 bool "Rockchip RK322x clock controller support"
55 bool "Rockchip RK3288 clock controller support"
62 bool "Rockchip RK3308 clock controller support"
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