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Searched refs:cr30 (Results 1 – 7 of 7) sorted by relevance

/drivers/video/fbdev/i810/
Di810.h216 u8 cr13, cr15, cr16, cr30; member
240 u8 cr30, cr31, cr32, cr33, cr35; member
Di810_dvt.c271 total = (std_modes[mode].cr06 | (std_modes[mode].cr30 & 0xF) << 8) + 2; in i810fb_fill_var_timings()
Di810_gtf.c162 par->regs.cr30 = (u8) ((n >> 8) & 0x0F); in i810fb_encode_registers()
Di810_main.c304 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30); in i810_load_vgax()
500 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i)); in i810_restore_vgax()
615 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio); in i810_save_vgax()
/drivers/video/fbdev/sis/
Dsis_main.c3488 u8 cr30, cr31; in sisfb_check_engine_and_sync() local
3495 cr30 = SiS_GetReg(SISSR, IND_SIS_PCI_ADDRESS_SET); in sisfb_check_engine_and_sync()
3498 if((cr30 & SIS_MEM_MAP_IO_ENABLE) && (cr31 & 0x42)) { in sisfb_check_engine_and_sync()
3514 cr30 = SiS_GetReg(SISSR, 0x26); in sisfb_check_engine_and_sync()
3515 if((cr30 & 0xe0) && (!(cr30 & 0x01))) { in sisfb_check_engine_and_sync()
3526 u8 cr30 = 0, cr31 = 0, cr33 = 0, cr35 = 0, cr38 = 0; in sisfb_pre_setmode() local
3573 cr30 |= SIS_SIMULTANEOUS_VIEW_ENABLE; in sisfb_pre_setmode()
3577 cr30 |= (0x80 | SIS_SIMULTANEOUS_VIEW_ENABLE); in sisfb_pre_setmode()
3592 cr30 |= 0x80; in sisfb_pre_setmode()
3594 cr30 |= SIS_SIMULTANEOUS_VIEW_ENABLE; in sisfb_pre_setmode()
[all …]
/drivers/parport/
Dparport_pc.c1031 int cr30, cr60, cr61, cr70, cr74, crf0; in show_parconfig_winbond() local
1054 cr30 = inb(io + 1); in show_parconfig_winbond()
1069 cr30, cr60, cr61, cr70, cr74, crf0); in show_parconfig_winbond()
1071 (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); in show_parconfig_winbond()
1082 if (cr30 & 0x01) { /* the settings can be interrogated later ... */ in show_parconfig_winbond()
/drivers/video/fbdev/
Ds3fb.c1064 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification() local
1068 if ((cr30 == 0xE0) || (cr30 == 0xE1)) { in s3_identification()