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Searched refs:crtc_h (Results 1 – 25 of 66) sorted by relevance

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/drivers/gpu/drm/armada/
Darmada_trace.h33 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
35 TP_ARGS(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h),
43 __field(unsigned int, crtc_h)
56 __entry->crtc_h = crtc_h;
65 __entry->crtc_w, __entry->crtc_h,
Darmada_overlay.c260 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, in armada_overlay_plane_update() argument
269 crtc_x, crtc_y, crtc_w, crtc_h, in armada_overlay_plane_update()
290 plane_state->crtc_h = crtc_h; in armada_overlay_plane_update()
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_plane.c51 unsigned int crtc_w, unsigned int crtc_h,
140 new_state->crtc_w, new_state->crtc_h, in mdp4_plane_atomic_update()
212 unsigned int crtc_w, unsigned int crtc_h, in mdp4_plane_mode_set() argument
241 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); in mdp4_plane_mode_set()
250 if (src_h > (crtc_h * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
260 if (crtc_h > (src_h * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
281 if (src_h != crtc_h) { in mdp4_plane_mode_set()
287 if (crtc_h > src_h) in mdp4_plane_mode_set()
289 else if (crtc_h <= (src_h / 4)) in mdp4_plane_mode_set()
294 src_h, crtc_h); in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c95 uint32_t crtc_w, uint32_t crtc_h) in verify_scaling() argument
97 if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { in verify_scaling()
99 src_w, src_h, crtc_w, crtc_h); in verify_scaling()
115 unsigned int crtc_w, unsigned int crtc_h, in nv10_update_plane() argument
140 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
159 nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); in nv10_update_plane()
161 nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); in nv10_update_plane()
365 unsigned int crtc_w, unsigned int crtc_h, in nv04_update_plane() argument
385 ret = verify_scaling(fb, 0, src_x, src_y, src_w, src_h, crtc_w, crtc_h); in nv04_update_plane()
408 nvif_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w); in nv04_update_plane()
[all …]
/drivers/gpu/drm/selftests/
Dtest-drm_plane_helper.c52 unsigned crtc_w, unsigned crtc_h) in set_crtc() argument
57 plane_state->crtc_h = crtc_h; in set_crtc()
62 unsigned crtc_w, unsigned crtc_h) in check_crtc_eq() argument
67 drm_rect_height(&plane_state->dst) != crtc_h) { in check_crtc_eq()
/drivers/gpu/drm/shmobile/
Dshmob_drm_plane.c34 unsigned int crtc_h; member
132 (splane->crtc_h << LDBBSSZR_BVSS_SHIFT) | in __shmob_drm_plane_setup()
172 unsigned int crtc_w, unsigned int crtc_h, in shmob_drm_plane_update() argument
188 if (src_w >> 16 != crtc_w || src_h >> 16 != crtc_h) { in shmob_drm_plane_update()
200 splane->crtc_h = crtc_h; in shmob_drm_plane_update()
/drivers/gpu/drm/
Ddrm_plane.c772 uint32_t crtc_w, uint32_t crtc_h, in __setplane_check() argument
796 crtc_h > INT_MAX || in __setplane_check()
797 crtc_y > INT_MAX - (int32_t) crtc_h) { in __setplane_check()
799 crtc_w, crtc_h, crtc_x, crtc_y); in __setplane_check()
845 uint32_t crtc_w, uint32_t crtc_h, in __setplane_internal() argument
869 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_internal()
876 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_internal()
898 uint32_t crtc_w, uint32_t crtc_h, in __setplane_atomic() argument
919 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_atomic()
925 crtc_x, crtc_y, crtc_w, crtc_h, in __setplane_atomic()
[all …]
Ddrm_plane_helper.c124 .crtc_h = drm_rect_height(dst), in drm_plane_helper_check_update()
151 unsigned int crtc_w, unsigned int crtc_h, in drm_primary_helper_update() argument
173 .y2 = crtc_y + crtc_h, in drm_primary_helper_update()
/drivers/gpu/drm/vc4/
Dvc4_plane.c322 vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h * in vc4_plane_margins_adj()
326 if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h) in vc4_plane_margins_adj()
371 vc4_state->crtc_h = state->dst.y2 - state->dst.y1; in vc4_plane_setup_clipping_and_scaling()
380 vc4_state->crtc_h); in vc4_plane_setup_clipping_and_scaling()
396 vc4_state->crtc_h); in vc4_plane_setup_clipping_and_scaling()
505 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
518 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
571 vc4_state->crtc_h); in vc4_plane_calc_load()
575 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w; in vc4_plane_calc_load()
854 VC4_SET_FIELD(vc4_state->crtc_h, in vc4_plane_mode_set()
[all …]
/drivers/gpu/drm/exynos/
Dexynos_drm_plane.c63 unsigned int crtc_w, crtc_h; in exynos_plane_mode_set() local
78 crtc_h = state->crtc_h; in exynos_plane_mode_set()
87 exynos_state->v_ratio = (src_h << 16) / crtc_h; in exynos_plane_mode_set()
91 actual_h = exynos_plane_get_size(crtc_y, crtc_h, mode->vdisplay); in exynos_plane_mode_set()
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c50 unsigned int crtc_h; member
293 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { in atmel_hlcdc_plane_setup_scaler()
305 state->crtc_h, in atmel_hlcdc_plane_setup_scaler()
316 state->crtc_h < state->src_h ? in atmel_hlcdc_plane_setup_scaler()
323 yfactor = (1024 * state->src_h) / state->crtc_h; in atmel_hlcdc_plane_setup_scaler()
341 state->crtc_h)); in atmel_hlcdc_plane_update_pos_and_size()
559 if (ovl_state->crtc_h * ovl_state->crtc_w < disc_h * disc_w) in atmel_hlcdc_plane_prepare_disc_area()
564 disc_h = ovl_state->crtc_h; in atmel_hlcdc_plane_prepare_disc_area()
628 hstate->crtc_h = drm_rect_height(&s->dst); in atmel_hlcdc_plane_atomic_check()
703 mode->vdisplay != hstate->crtc_h)) in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_plane.c241 ((state->src_h >> 16) != state->crtc_h)) in mdp5_plane_atomic_check_with_state()
410 plane->state->crtc_h != new_plane_state->crtc_h || in mdp5_plane_atomic_async_check()
769 unsigned int crtc_w, unsigned int crtc_h, in mdp5_hwpipe_mode_set() argument
793 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); in mdp5_hwpipe_mode_set()
876 unsigned int crtc_w, crtc_h; in mdp5_plane_mode_set() local
899 crtc_h = drm_rect_height(dest); in mdp5_plane_mode_set()
912 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); in mdp5_plane_mode_set()
930 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); in mdp5_plane_mode_set()
937 calc_pixel_ext(format, src_h, crtc_h, step.y, in mdp5_plane_mode_set()
945 config |= get_scale_config(format, src_h, crtc_h, false); in mdp5_plane_mode_set()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_sprite.c433 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); in vlv_update_plane() local
443 crtc_h--; in vlv_update_plane()
454 (crtc_h << 16) | crtc_w); in vlv_update_plane()
850 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); in ivb_update_plane() local
864 crtc_h--; in ivb_update_plane()
866 if (crtc_w != src_w || crtc_h != src_h) in ivb_update_plane()
876 intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w); in ivb_update_plane()
1178 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); in g4x_update_plane() local
1192 crtc_h--; in g4x_update_plane()
1194 if (crtc_w != src_w || crtc_h != src_h) in g4x_update_plane()
[all …]
Dintel_cursor.c615 unsigned int crtc_w, unsigned int crtc_h, in intel_legacy_cursor_update() argument
662 old_plane_state->uapi.crtc_h != crtc_h || in intel_legacy_cursor_update()
685 new_plane_state->uapi.crtc_h = crtc_h; in intel_legacy_cursor_update()
737 crtc_x, crtc_y, crtc_w, crtc_h, in intel_legacy_cursor_update()
/drivers/gpu/drm/tilcdc/
Dtilcdc_plane.c52 crtc_state->mode.vdisplay != new_state->crtc_h) { in tilcdc_plane_atomic_check()
56 new_state->crtc_w, new_state->crtc_h); in tilcdc_plane_atomic_check()
/drivers/gpu/drm/sun4i/
Dsun4i_frontend.c503 state->crtc_w, state->crtc_h); in sun4i_frontend_update_coord()
517 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w)); in sun4i_frontend_update_coord()
519 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w)); in sun4i_frontend_update_coord()
527 (luma_height << 16) / state->crtc_h); in sun4i_frontend_update_coord()
529 (chroma_height << 16) / state->crtc_h); in sun4i_frontend_update_coord()
Dsun4i_backend.c177 state->crtc_w, state->crtc_h); in sun4i_backend_update_layer_coord()
180 state->crtc_h)); in sun4i_backend_update_layer_coord()
185 state->crtc_w, state->crtc_h); in sun4i_backend_update_layer_coord()
188 state->crtc_h)); in sun4i_backend_update_layer_coord()
417 src_w, src_h, state->crtc_w, state->crtc_h); in sun4i_backend_plane_uses_scaler()
419 if ((state->crtc_h != src_h) || (state->crtc_w != src_w)) in sun4i_backend_plane_uses_scaler()
/drivers/gpu/drm/ingenic/
Dingenic-ipu.c284 state->crtc_h != oldstate->crtc_h; in osd_changed()
434 | newstate->crtc_h << JZ_IPU_OUT_GS_H_LSB); in ingenic_ipu_plane_atomic_update()
521 newstate->crtc_w, newstate->crtc_h, in ingenic_ipu_plane_atomic_update()
555 new_plane_state->crtc_y + new_plane_state->crtc_h > crtc_state->mode.vdisplay) in ingenic_ipu_plane_atomic_check()
590 for (denom_h = yres, num_h = new_plane_state->crtc_h; num_h <= max_h; num_h++) in ingenic_ipu_plane_atomic_check()
/drivers/gpu/drm/hisilicon/kirin/
Dkirin_drm_ade.c711 unsigned int crtc_h, u32 src_x, in ade_update_channel() argument
723 crtc_x, crtc_y, crtc_w, crtc_h); in ade_update_channel()
774 u32 crtc_h = new_plane_state->crtc_h; in ade_plane_atomic_check() local
788 if (src_w != crtc_w || src_h != crtc_h) { in ade_plane_atomic_check()
800 crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay) in ade_plane_atomic_check()
815 new_state->crtc_w, new_state->crtc_h, in ade_plane_atomic_update()
/drivers/gpu/drm/imx/dcss/
Ddcss-plane.c195 new_plane_state->crtc_y + new_plane_state->crtc_h > vdisplay) && in dcss_plane_atomic_check()
255 state->crtc_h != old_state->crtc_h || in dcss_plane_needs_setup()
/drivers/gpu/drm/imx/
Dipuv3-plane.h40 unsigned int crtc_w, unsigned int crtc_h,
/drivers/gpu/drm/mediatek/
Dmtk_drm_plane.c151 plane->state->crtc_h = new_state->crtc_h; in mtk_plane_atomic_async_update()
/drivers/gpu/drm/arm/
Dmalidp_planes.c297 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { in malidp_se_check_scaling()
552 (new_plane_state->crtc_h > mp->hwdev->max_line_size) || in malidp_de_plane_check()
554 (new_plane_state->crtc_h < mp->hwdev->min_line_size)) in malidp_de_plane_check()
597 new_plane_state->crtc_h, in malidp_de_plane_check()
824 dest_h = new_state->crtc_h; in malidp_de_plane_update()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_trace.h239 __field(uint32_t, crtc_h)
268 __entry->crtc_h = state->crtc_h;
298 __entry->crtc_y, __entry->crtc_w, __entry->crtc_h,
/drivers/gpu/drm/sti/
Dsti_gdp.c643 dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y); in sti_gdp_atomic_check()
732 (oldstate->crtc_h == newstate->crtc_h) && in sti_gdp_atomic_update()
757 dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y); in sti_gdp_atomic_update()

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