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Searched refs:csr0 (Results 1 – 14 of 14) sorted by relevance

/drivers/net/ethernet/amd/
Dariadne.c244 int csr0, boguscnt; in ariadne_interrupt() local
255 while ((csr0 = lance->RDP) & (ERR | RINT | TINT) && --boguscnt >= 0) { in ariadne_interrupt()
257 lance->RDP = csr0 & ~(INEA | TDMD | STOP | STRT | INIT); in ariadne_interrupt()
262 csr0, lance->RDP); in ariadne_interrupt()
263 if (csr0 & INTR) in ariadne_interrupt()
265 if (csr0 & INEA) in ariadne_interrupt()
267 if (csr0 & RXON) in ariadne_interrupt()
269 if (csr0 & TXON) in ariadne_interrupt()
271 if (csr0 & TDMD) in ariadne_interrupt()
273 if (csr0 & STOP) in ariadne_interrupt()
[all …]
Dni65.c721 int csr0 = CSR0_INEA; in ni65_stop_start() local
761 writedatareg(CSR0_STRT | csr0); in ni65_stop_start()
770 writedatareg(CSR0_TDMD | CSR0_INEA | csr0); in ni65_stop_start()
783 writedatareg(CSR0_STRT | csr0); in ni65_stop_start()
873 int csr0 = 0; in ni65_interrupt() local
883 csr0 = inw(PORT+L_DATAREG); in ni65_interrupt()
886 writedatareg( (csr0 & CSR0_CLRALL) ); /* ack interrupts, disable int. */ in ni65_interrupt()
888 writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */ in ni65_interrupt()
891 if(!(csr0 & (CSR0_ERR | CSR0_RINT | CSR0_TINT))) in ni65_interrupt()
894 if(csr0 & CSR0_RINT) /* RECV-int? */ in ni65_interrupt()
[all …]
D7990.c445 int csr0; in lance_interrupt() local
450 csr0 = READRDP(lp); in lance_interrupt()
454 if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */ in lance_interrupt()
460 WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT)); in lance_interrupt()
462 if ((csr0 & LE_C0_ERR)) { in lance_interrupt()
467 if (csr0 & LE_C0_RINT) in lance_interrupt()
470 if (csr0 & LE_C0_TINT) in lance_interrupt()
474 if (csr0 & LE_C0_BABL) in lance_interrupt()
476 if (csr0 & LE_C0_MISS) in lance_interrupt()
478 if (csr0 & LE_C0_MERR) { in lance_interrupt()
[all …]
Da2065.c415 int csr0; in lance_interrupt() local
418 csr0 = ll->rdp; in lance_interrupt()
420 if (!(csr0 & LE_C0_INTR)) /* Check if any interrupt has */ in lance_interrupt()
424 ll->rdp = csr0 & ~(LE_C0_INEA | LE_C0_TDMD | LE_C0_STOP | LE_C0_STRT | in lance_interrupt()
427 if (csr0 & LE_C0_ERR) { in lance_interrupt()
432 if (csr0 & LE_C0_RINT) in lance_interrupt()
435 if (csr0 & LE_C0_TINT) in lance_interrupt()
439 if (csr0 & LE_C0_BABL) in lance_interrupt()
441 if (csr0 & LE_C0_MISS) in lance_interrupt()
443 if (csr0 & LE_C0_MERR) { in lance_interrupt()
[all …]
Dsun3lance.c655 int csr0; in lance_interrupt() local
661 csr0 = DREG; in lance_interrupt()
664 DREG = csr0 & (CSR0_TINT | CSR0_RINT | CSR0_IDON); in lance_interrupt()
667 if(csr0 & CSR0_ERR) in lance_interrupt()
672 dev->name, csr0, DREG )); in lance_interrupt()
674 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ in lance_interrupt()
733 if (csr0 & CSR0_RINT) /* Rx interrupt */ in lance_interrupt()
737 if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */ in lance_interrupt()
738 if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */ in lance_interrupt()
739 if (csr0 & CSR0_MERR) { in lance_interrupt()
[all …]
Datarilance.c851 int csr0, boguscnt = 10; in lance_interrupt() local
865 while( ((csr0 = DREG) & (CSR0_ERR | CSR0_TINT | CSR0_RINT)) && in lance_interrupt()
869 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP | in lance_interrupt()
873 dev->name, csr0, DREG )); in lance_interrupt()
875 if (csr0 & CSR0_RINT) /* Rx interrupt */ in lance_interrupt()
878 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */ in lance_interrupt()
902 dev->name, csr0 )); in lance_interrupt()
936 if (csr0 & CSR0_BABL) dev->stats.tx_errors++; /* Tx babble. */ in lance_interrupt()
937 if (csr0 & CSR0_MISS) dev->stats.rx_errors++; /* Missed a Rx frame. */ in lance_interrupt()
938 if (csr0 & CSR0_MERR) { in lance_interrupt()
[all …]
Dlance.c1026 int csr0, ioaddr, boguscnt=10; in lance_interrupt() local
1035 while ((csr0 = inw(dev->base_addr + LANCE_DATA)) & 0x8600 && in lance_interrupt()
1038 outw(csr0 & ~0x004f, dev->base_addr + LANCE_DATA); in lance_interrupt()
1044 dev->name, csr0, inw(dev->base_addr + LANCE_DATA)); in lance_interrupt()
1046 if (csr0 & 0x0400) /* Rx interrupt */ in lance_interrupt()
1049 if (csr0 & 0x0200) { /* Tx-done interrupt */ in lance_interrupt()
1076 dev->name, csr0); in lance_interrupt()
1113 if (csr0 & 0x4000) in lance_interrupt()
1115 if (csr0 & 0x1000) in lance_interrupt()
1117 if (csr0 & 0x0800) { in lance_interrupt()
[all …]
Ddeclance.c739 int csr0; in lance_interrupt() local
742 csr0 = ll->rdp; in lance_interrupt()
745 writereg(&ll->rdp, csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT)); in lance_interrupt()
747 if ((csr0 & LE_C0_ERR)) { in lance_interrupt()
752 if (csr0 & LE_C0_RINT) in lance_interrupt()
755 if (csr0 & LE_C0_TINT) in lance_interrupt()
758 if (csr0 & LE_C0_BABL) in lance_interrupt()
761 if (csr0 & LE_C0_MISS) in lance_interrupt()
764 if (csr0 & LE_C0_MERR) { in lance_interrupt()
765 printk("%s: Memory error, status %04x\n", dev->name, csr0); in lance_interrupt()
Dsunlance.c814 int csr0; in lance_interrupt() local
817 csr0 = sbus_readw(lp->lregs + RDP); in lance_interrupt()
820 sbus_writew(csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT), in lance_interrupt()
823 if ((csr0 & LE_C0_ERR) != 0) { in lance_interrupt()
830 if (csr0 & LE_C0_RINT) in lance_interrupt()
833 if (csr0 & LE_C0_TINT) in lance_interrupt()
836 if (csr0 & LE_C0_BABL) in lance_interrupt()
839 if (csr0 & LE_C0_MISS) in lance_interrupt()
842 if (csr0 & LE_C0_MERR) { in lance_interrupt()
847 dev->name, csr0, addr & 0xffffff); in lance_interrupt()
[all …]
Dpcnet32.c1430 int i, csr0; in pcnet32_get_regs() local
1439 csr0 = a->read_csr(ioaddr, CSR0); in pcnet32_get_regs()
1440 if (!(csr0 & CSR0_STOP)) /* If not stopped */ in pcnet32_get_regs()
1477 if (!(csr0 & CSR0_STOP)) /* If not stopped */ in pcnet32_get_regs()
2547 u16 csr0; in pcnet32_interrupt() local
2555 csr0 = lp->a->read_csr(ioaddr, CSR0); in pcnet32_interrupt()
2556 while ((csr0 & 0x8f00) && --boguscnt >= 0) { in pcnet32_interrupt()
2557 if (csr0 == 0xffff) in pcnet32_interrupt()
2560 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); in pcnet32_interrupt()
2564 csr0, lp->a->read_csr(ioaddr, CSR0)); in pcnet32_interrupt()
[all …]
/drivers/net/ethernet/dec/tulip/
Dtulip_core.c77 static int csr0 = 0x01A00000 | 0xE000; variable
79 static int csr0 = 0x01A00000 | 0x8000; variable
85 static int csr0 = 0x01A00000 | 0x9000; variable
87 static int csr0 = 0x01A00000 | 0x4800; variable
89 static int csr0 = 0x00200000 | 0x4000; variable
91 static int csr0; variable
105 module_param(csr0, int, 0);
314 iowrite32(tp->csr0, ioaddr + CSR0); in tulip_up()
1186 u32 csr0; in tulip_mwi_config() local
1191 tp->csr0 = csr0 = 0; in tulip_mwi_config()
[all …]
Dtulip.h437 unsigned int csr0; /* CSR0 setting. */ member
Dde4x5.c828 s32 csr0; /* Saved Bus Mode Register */ member
3739 lp->cache.csr0 = inl(DE4X5_BMR); in de4x5_cache_state()
3745 outl(lp->cache.csr0, DE4X5_BMR); in de4x5_cache_state()
/drivers/usb/mtu3/
Dmtu3_core.c410 u32 csr0, csr1, csr2; in mtu3_config_ep() local
424 csr0 = TX_TXMAXPKTSZ(mep->maxp); in mtu3_config_ep()
425 csr0 |= TX_DMAREQEN; in mtu3_config_ep()
451 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0); in mtu3_config_ep()
460 csr0 = RX_RXMAXPKTSZ(mep->maxp); in mtu3_config_ep()
461 csr0 |= RX_DMAREQEN; in mtu3_config_ep()
487 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0); in mtu3_config_ep()
497 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2); in mtu3_config_ep()