Searched refs:ctl0 (Results 1 – 4 of 4) sorted by relevance
112 int i, int len, u32 ctl0) in bgmac_dma_tx_add_buf() argument119 ctl0 |= BGMAC_DESC_CTL0_EOT; in bgmac_dma_tx_add_buf()127 dma_desc->ctl0 = cpu_to_le32(ctl0); in bgmac_dma_tx_add_buf()251 u32 ctl0, ctl1; in bgmac_dma_tx_free() local257 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0); in bgmac_dma_tx_free()260 if (ctl0 & BGMAC_DESC_CTL0_SOF) in bgmac_dma_tx_free()381 u32 ctl0 = 0, ctl1 = 0; in bgmac_dma_rx_setup_desc() local384 ctl0 |= BGMAC_DESC_CTL0_EOT; in bgmac_dma_rx_setup_desc()393 dma_desc->ctl0 = cpu_to_le32(ctl0); in bgmac_dma_rx_setup_desc()
403 __le32 ctl0; member
39 u8 ctl0; /* offset in regs of ctl for CE0 */ member52 .ctl0 = 0x10,61 .ctl0 = 0x04,70 .ctl0 = 0x10,79 .ctl0 = 0x10,809 chip->ctl = controller->regs + info->ctl0 + cs * 4; in aspeed_smc_setup_flash()
184 u32 ctl0 = 0, ctl1 = 0; in op64_fill_descriptor() local196 ctl0 |= B43_DMA64_DCTL0_DTABLEEND; in op64_fill_descriptor()198 ctl0 |= B43_DMA64_DCTL0_FRAMESTART; in op64_fill_descriptor()200 ctl0 |= B43_DMA64_DCTL0_FRAMEEND; in op64_fill_descriptor()202 ctl0 |= B43_DMA64_DCTL0_IRQ; in op64_fill_descriptor()207 desc->dma64.control0 = cpu_to_le32(ctl0); in op64_fill_descriptor()