Searched refs:dcfclkv_mid0p72 (Results 1 – 2 of 2) sorted by relevance
77 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */614 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;799 v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72; in dcn_validate_bandwidth()885 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72; in dcn_validate_bandwidth()1412 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) { in dcn_find_normalized_clock_vdd_Level()1460 dcf_clk = dc->dcn_soc->dcfclkv_mid0p72*1000; in dcn_find_dcfclk_suits_all()1537 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib()1656 dc->dcn_soc->dcfclkv_mid0p72 * 1000, in dcn_bw_sync_calcs_and_dml()
117 float dcfclkv_mid0p72; member554 float dcfclkv_mid0p72; /*MHz*/ member