| /drivers/gpu/drm/mediatek/ |
| D | mtk_hdmi_ddc.c | 62 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_set_bit() argument
65 writel(readl(ddc->regs + offset) | val, ddc->regs + offset); in sif_set_bit()
68 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_clr_bit() argument
71 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); in sif_clr_bit()
74 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_bit_is_set() argument
77 return (readl(ddc->regs + offset) & val) == val; in sif_bit_is_set()
80 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_write_mask() argument
86 tmp = readl(ddc->regs + offset); in sif_write_mask()
89 writel(tmp, ddc->regs + offset); in sif_write_mask()
92 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc, in sif_read_mask() argument
[all …]
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| /drivers/gpu/drm/amd/display/dc/gpio/ |
| D | gpio_service.c | 468 struct ddc *dal_gpio_create_ddc( in dal_gpio_create_ddc()
476 struct ddc *ddc; in dal_gpio_create_ddc() local
481 ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL); in dal_gpio_create_ddc()
483 if (!ddc) { in dal_gpio_create_ddc()
488 ddc->pin_data = dal_gpio_create( in dal_gpio_create_ddc()
491 if (!ddc->pin_data) { in dal_gpio_create_ddc()
496 ddc->pin_clock = dal_gpio_create( in dal_gpio_create_ddc()
499 if (!ddc->pin_clock) { in dal_gpio_create_ddc()
504 ddc->hw_info = *info; in dal_gpio_create_ddc()
506 ddc->ctx = service->ctx; in dal_gpio_create_ddc()
[all …]
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| D | hw_ddc.c | 42 ddc->shifts->field_name, ddc->masks->field_name
45 ddc->base.base.ctx
47 (ddc->regs->reg)
73 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); in set_config() local
80 hw_gpio = &ddc->base; in set_config()
92 switch (config_data->config.ddc.type) { in set_config()
139 if (config_data->config.ddc.data_en_bit_present || in set_config()
140 config_data->config.ddc.clock_en_bit_present) in set_config()
152 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { in set_config()
156 if (ddc->regs->phy_aux_cntl != 0) { in set_config()
[all …]
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| D | gpio_base.c | 71 if (!gpio->hw_container.ddc) { in dal_gpio_open_ex()
240 return gpio->hw_container.ddc; in dal_gpio_get_ddc()
292 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
295 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
326 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
327 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
331 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
332 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_ddc.c | 244 static void ddc_service_destruct(struct ddc_service *ddc) in ddc_service_destruct() argument
246 if (ddc->ddc_pin) in ddc_service_destruct()
247 dal_gpio_destroy_ddc(&ddc->ddc_pin); in ddc_service_destruct()
250 void dal_ddc_service_destroy(struct ddc_service **ddc) in dal_ddc_service_destroy() argument
252 if (!ddc || !*ddc) { in dal_ddc_service_destroy()
256 ddc_service_destruct(*ddc); in dal_ddc_service_destroy()
257 kfree(*ddc); in dal_ddc_service_destroy()
258 *ddc = NULL; in dal_ddc_service_destroy()
261 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc) in dal_ddc_service_get_type() argument
267 struct ddc_service *ddc, in dal_ddc_service_set_transaction_type() argument
[all …]
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| /drivers/gpu/drm/sun4i/ |
| D | sun4i_hdmi_ddc_clk.c | 65 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_round_rate() local
67 return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, in sun4i_ddc_round_rate()
68 ddc->m_offset, NULL, NULL); in sun4i_ddc_round_rate()
74 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_recalc_rate() local
78 regmap_field_read(ddc->reg, ®); in sun4i_ddc_recalc_rate()
82 return (((parent_rate / ddc->pre_div) / 10) >> n) / in sun4i_ddc_recalc_rate()
83 (m + ddc->m_offset); in sun4i_ddc_recalc_rate()
89 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_set_rate() local
92 sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, in sun4i_ddc_set_rate()
93 ddc->m_offset, &div_m, &div_n); in sun4i_ddc_set_rate()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_i2c_sw.c | 42 struct ddc *ddc, in read_bit_from_ddc() argument
48 dal_gpio_get_value(ddc->pin_data, &value); in read_bit_from_ddc()
50 dal_gpio_get_value(ddc->pin_clock, &value); in read_bit_from_ddc()
56 struct ddc *ddc, in write_bit_to_ddc() argument
63 dal_gpio_set_value(ddc->pin_data, value); in write_bit_to_ddc()
65 dal_gpio_set_value(ddc->pin_clock, value); in write_bit_to_ddc()
72 dal_ddc_close(dce_i2c_sw->ddc); in release_engine_dce_sw()
73 dce_i2c_sw->ddc = NULL; in release_engine_dce_sw()
78 struct ddc *ddc, in wait_for_scl_high_sw() argument
87 if (read_bit_from_ddc(ddc, SCL)) in wait_for_scl_high_sw()
[all …]
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| D | dce_aux.c | 86 dal_ddc_close(engine->ddc); in release_engine()
88 engine->ddc = NULL; in release_engine()
279 EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE, in submit_channel_request()
402 struct ddc *ddc) in acquire() argument
409 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, in acquire()
416 dal_ddc_close(ddc); in acquire()
420 engine->ddc = ddc; in acquire()
435 static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc, in dce_aux_configure_timeout() argument
443 struct ddc *ddc_pin = ddc->ddc_pin; in dce_aux_configure_timeout()
444 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_configure_timeout()
[all …]
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| D | dce_i2c.c | 30 struct ddc *ddc, in dce_i2c_submit_command() argument
36 if (!ddc) { in dce_i2c_submit_command()
46 dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc); in dce_i2c_submit_command()
49 return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw); in dce_i2c_submit_command()
51 dce_i2c_sw.ctx = ddc->ctx; in dce_i2c_submit_command()
52 if (dce_i2c_engine_acquire_sw(&dce_i2c_sw, ddc)) { in dce_i2c_submit_command()
53 return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw); in dce_i2c_submit_command()
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| D | dce_i2c_sw.h | 36 struct ddc *ddc; member
48 struct ddc *ddc,
54 struct ddc *ddc_handle);
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | dc_link_ddc.h | 77 void dal_ddc_service_destroy(struct ddc_service **ddc);
79 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc);
82 struct ddc_service *ddc,
85 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
88 struct ddc_service *ddc,
92 struct ddc_service *ddc,
99 bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
102 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
106 bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
109 bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
[all …]
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| /drivers/gpu/drm/amd/display/include/ |
| D | gpio_service_interface.h | 71 struct ddc *dal_gpio_create_ddc(
78 struct ddc **ddc);
103 struct ddc *ddc,
108 struct ddc *ddc,
112 const struct ddc *ddc);
115 struct ddc *ddc,
119 struct ddc *ddc);
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| /drivers/gpu/drm/tegra/ |
| D | output.c | 35 else if (output->ddc) in tegra_output_connector_get_modes()
36 edid = drm_get_edid(connector, output->ddc); in tegra_output_connector_get_modes()
96 struct device_node *ddc, *panel; in tegra_output_probe() local
125 ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0); in tegra_output_probe()
126 if (ddc) { in tegra_output_probe()
127 output->ddc = of_get_i2c_adapter_by_node(ddc); in tegra_output_probe()
128 of_node_put(ddc); in tegra_output_probe()
130 if (!output->ddc) { in tegra_output_probe()
186 if (output->ddc) in tegra_output_remove()
187 i2c_put_adapter(output->ddc); in tegra_output_remove()
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| /drivers/gpu/drm/zte/ |
| D | zx_vga.c | 37 struct zx_vga_i2c *ddc; member
88 edid = drm_get_edid(connector, &vga->ddc->adap); in zx_vga_connector_get_modes()
167 &vga->ddc->adap); in zx_vga_register()
285 struct zx_vga_i2c *ddc = vga->ddc; in zx_vga_i2c_xfer() local
289 mutex_lock(&ddc->lock); in zx_vga_i2c_xfer()
304 mutex_unlock(&ddc->lock); in zx_vga_i2c_xfer()
323 struct zx_vga_i2c *ddc; in zx_vga_ddc_register() local
326 ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL); in zx_vga_ddc_register()
327 if (!ddc) in zx_vga_ddc_register()
330 vga->ddc = ddc; in zx_vga_ddc_register()
[all …]
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| D | zx_hdmi.c | 41 struct zx_hdmi_i2c *ddc; member
264 edid = drm_get_edid(connector, &hdmi->ddc->adap); in zx_hdmi_connector_get_modes()
321 &hdmi->ddc->adap); in zx_hdmi_register()
564 struct zx_hdmi_i2c *ddc = hdmi->ddc; in zx_hdmi_i2c_xfer() local
567 mutex_lock(&ddc->lock); in zx_hdmi_i2c_xfer()
592 mutex_unlock(&ddc->lock); in zx_hdmi_i2c_xfer()
610 struct zx_hdmi_i2c *ddc; in zx_hdmi_ddc_register() local
613 ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL); in zx_hdmi_ddc_register()
614 if (!ddc) in zx_hdmi_ddc_register()
617 hdmi->ddc = ddc; in zx_hdmi_ddc_register()
[all …]
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| /drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| D | hw_factory_dce110.c | 116 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
120 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
121 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
124 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
132 ddc->shifts = &ddc_shift; in define_ddc_registers()
133 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| D | hw_factory_dce80.c | 120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
| D | hw_factory_dce60.c | 120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| D | hw_factory_dce120.c | 133 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
137 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
138 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
141 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
142 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
149 ddc->shifts = &ddc_shift; in define_ddc_registers()
150 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| D | hw_factory_dcn10.c | 165 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
169 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
170 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
173 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
174 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
181 ddc->shifts = &ddc_shift; in define_ddc_registers()
182 ddc->masks = &ddc_mask; in define_ddc_registers()
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| /drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| D | hw_factory_dcn21.c | 173 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
177 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
178 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
181 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
182 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
190 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
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| /drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| D | hw_factory_dcn20.c | 183 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
187 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
188 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
191 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
192 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
199 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
200 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
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| /drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| D | hw_factory_dcn30.c | 201 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
205 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
206 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
209 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
210 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
217 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
218 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
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| /drivers/gpu/drm/bridge/ |
| D | display-connector.c | 53 if (conn->bridge.ddc && drm_probe_ddc(conn->bridge.ddc)) in display_connector_detect()
88 return drm_get_edid(connector, conn->bridge.ddc); in display_connector_get_edid()
306 conn->bridge.ddc = of_get_i2c_adapter_by_node(phandle); in display_connector_probe()
308 if (!conn->bridge.ddc) in display_connector_probe()
351 if (conn->bridge.ddc) in display_connector_probe()
363 conn->bridge.ddc ? "with" : "without", in display_connector_probe()
381 if (!IS_ERR(conn->bridge.ddc)) in display_connector_remove()
382 i2c_put_adapter(conn->bridge.ddc); in display_connector_remove()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | aux_engine.h | 88 struct ddc *ddc; member
146 struct ddc_service *ddc,
175 struct ddc *ddc);
|