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Searched refs:div_mask (Results 1 – 25 of 27) sorted by relevance

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/drivers/clk/imx/
Dclk-pllv3.c51 u32 div_mask; member
114 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
142 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
162 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
197 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
219 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
284 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
352 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; in clk_pllv3_vf610_recalc_rate()
375 val &= ~pll->div_mask; /* clear bit for mfi=20 */ in clk_pllv3_vf610_set_rate()
377 val |= pll->div_mask; /* set bit for mfi=22 */ in clk_pllv3_vf610_set_rate()
[all …]
Dclk-fixup-div.c12 #define div_mask(d) ((1 << (d->width)) - 1) macro
66 if (value > div_mask(div)) in clk_fixup_div_set_rate()
67 value = div_mask(div); in clk_fixup_div_set_rate()
72 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
Dclk.h73 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
74 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
175 const char *parent_name, void __iomem *base, u32 div_mask);
/drivers/clk/rockchip/
Dclk-half-divider.c11 #define div_mask(width) ((1 << (width)) - 1) macro
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
46 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
88 bestdiv = div_mask(width); in clk_half_divider_bestdiv()
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
126 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
129 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
/drivers/clk/tegra/
Dclk-utils.c10 #define div_mask(w) ((1 << (w)) - 1) macro
39 if (divider_ux1 > div_mask(width)) in div_frac_get()
40 return div_mask(width); in div_frac_get()
Dclk-divider.c15 #define div_mask(d) ((1 << (d->width)) - 1) macro
17 #define get_max_div(d) div_mask(d)
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
96 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
/drivers/clk/
Dclk-vt8500.c23 unsigned int div_mask; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
121 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
126 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
150 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
169 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
173 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
181 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
262 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
264 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
/drivers/i2c/busses/
Di2c-brcmstb.c93 u32 div_mask; member
125 .div_mask = 0
130 .div_mask = 0
135 .div_mask = 0
140 .div_mask = 0
145 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
150 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
155 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
160 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
554 bsc_clk[i].div_mask); in brcmstb_i2c_set_bus_speed()
/drivers/clk/hisilicon/
Dclkdivider-hi6220.c19 #define div_mask(width) ((1 << (width)) - 1) macro
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
82 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
117 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
/drivers/clk/actions/
Dowl-factor.c158 val &= div_mask(factor_hw); in owl_factor_helper_recalc_rate()
193 if (val > div_mask(factor_hw)) in owl_factor_helper_set_rate()
194 val = div_mask(factor_hw); in owl_factor_helper_set_rate()
198 reg &= ~(div_mask(factor_hw) << factor_hw->shift); in owl_factor_helper_set_rate()
Dowl-factor.h58 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
/drivers/clk/samsung/
Dclk-cpu.c230 unsigned long div = 0, div_mask = DIV_MASK; in exynos_cpuclk_post_rate_change() local
252 div_mask |= E4210_DIV0_ATB_MASK; in exynos_cpuclk_post_rate_change()
255 exynos_set_safe_div(base, div, div_mask); in exynos_cpuclk_post_rate_change()
340 unsigned long div = 0, div_mask = DIV_MASK; in exynos5433_cpuclk_post_rate_change() local
351 exynos5433_set_safe_div(base, div, div_mask); in exynos5433_cpuclk_post_rate_change()
/drivers/sh/clk/
Dcpg.c123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
139 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
152 if (clk->div_mask == SH_CLK_DIV6_MSK) { in sh_clk_div_enable()
175 val |= clk->div_mask; in sh_clk_div_disable()
/drivers/clk/at91/
Dclk-peripheral.c170 periph->layout->div_mask | periph->layout->cmd | in clk_sam9x5_peripheral_enable()
172 field_prep(periph->layout->div_mask, periph->div) | in clk_sam9x5_peripheral_enable()
233 periph->div = field_get(periph->layout->div_mask, status); in clk_sam9x5_peripheral_recalc_rate()
450 if (layout->div_mask) in at91_clk_register_sam9x5_peripheral()
Dclk-sam9x60-pll.c313 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_prepare()
320 core->layout->div_mask | core->layout->endiv_mask, in sam9x60_div_pll_prepare()
403 for (divid = 1; divid < core->layout->div_mask; divid++) { in sam9x60_div_pll_compute_div()
462 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set_rate_chg()
469 core->layout->div_mask, in sam9x60_div_pll_set_rate_chg()
Dpmc.h59 u32 div_mask; member
96 u32 div_mask; member
Dat91sam9n12.c71 .div_mask = GENMASK(17, 16),
Dsama5d3.c37 .div_mask = GENMASK(17, 16),
Dat91sam9x5.c58 .div_mask = GENMASK(17, 16),
Dsam9x60.c54 .div_mask = GENMASK(7, 0),
/drivers/clk/mmp/
Dclk-mix.c29 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; in _get_maxdiv() local
34 return div_mask; in _get_maxdiv()
36 return 1 << div_mask; in _get_maxdiv()
43 return div_mask + 1; in _get_maxdiv()
/drivers/clk/nxp/
Dclk-lpc32xx.c920 #define div_mask(width) ((1 << (width)) - 1) macro
952 val &= div_mask(divider->width); in clk_divider_recalc_rate()
968 bestdiv &= div_mask(divider->width); in clk_divider_round_rate()
988 div_mask(divider->width) << divider->shift, in clk_divider_set_rate()
1475 static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) in lpc32xx_clk_div_quirk() argument
1481 if (!(val & div_mask)) { in lpc32xx_clk_div_quirk()
1483 val |= BIT(__ffs(div_mask)); in lpc32xx_clk_div_quirk()
1486 regmap_update_bits(clk_regmap, reg, gate | div_mask, val); in lpc32xx_clk_div_quirk()
/drivers/mfd/
Ddb8500-prcmu.c523 u32 div_mask; member
530 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
535 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
540 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
646 u32 div_mask; in prcmu_config_clkout() local
656 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; in prcmu_config_clkout()
661 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; in prcmu_config_clkout()
672 if (val & div_mask) { in prcmu_config_clkout()
679 if ((val & mask & ~div_mask) != bits) { in prcmu_config_clkout()
1535 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
[all …]
/drivers/staging/clocking-wizard/
Dclk-xlnx-clock-wizard.c50 #define div_mask(width) ((1 << (width)) - 1) macro
130 val &= div_mask(divider->width); in clk_wzrd_recalc_rate()
211 div = val & div_mask(divider->width); in clk_wzrd_recalc_ratef()
/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_14nm.c603 #define div_mask(width) ((1 << (width)) - 1) macro
617 val &= div_mask(width); in dsi_pll_14nm_postdiv_recalc_rate()
659 val &= ~(div_mask(width) << shift); in dsi_pll_14nm_postdiv_set_rate()

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