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Searched refs:dml_min (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/
Ddml_inline_defs.h32 static inline double dml_min(double a, double b) in dml_min() function
39 return dml_min(dml_min(a, b), c); in dml_min3()
44 return dml_min(dml_min(a, b), dml_min(c, d)); in dml_min4()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_mode_vba_20.c237 mode_lib->vba.FabricAndDRAMBandwidth = dml_min( in dml20_recalculate()
257 dml_min( in adjust_ReturnBW()
280 dml_min( in adjust_ReturnBW()
1040 dml_min( in CalculateVMAndRowBytes()
1045 dml_min( in CalculateVMAndRowBytes()
1064 *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
1119 mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1128 mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1137 * dml_min( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1160 dml_min( in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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Ddisplay_mode_vba_20v2.c261 mode_lib->vba.FabricAndDRAMBandwidth = dml_min( in dml20v2_recalculate()
281 dml_min( in adjust_ReturnBW()
304 dml_min( in adjust_ReturnBW()
1100 dml_min( in CalculateVMAndRowBytes()
1105 dml_min( in CalculateVMAndRowBytes()
1124 *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
1179 mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1188 mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1197 * dml_min( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1220 dml_min( in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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Ddisplay_rq_dlg_calc_20.c134 * dml_min((double) recout_width, (double) hactive / 2.0) in get_refcyc_per_delivery()
610 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries in get_meta_and_pte_attr()
Ddisplay_rq_dlg_calc_20v2.c134 * dml_min((double) recout_width, (double) hactive / 2.0) in get_refcyc_per_delivery()
610 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries in get_meta_and_pte_attr()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c1624 max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
1625 max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
2003 …*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *…
2011 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
2067 double IdealFabricAndSDPPortBandwidthPerState = dml_min(
2072 v->ReturnBW = dml_min(
2076 v->ReturnBW = dml_min(
2105 v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
2109 v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
2114 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
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Ddisplay_rq_dlg_calc_31.c146 …* dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_… in get_refcyc_per_delivery()
785 vp_width = dml_min(full_src_vp_width, src_hactive_odm); in get_surf_rq_param()
788 vp_height = dml_min(full_src_vp_width, src_hactive_odm); in get_surf_rq_param()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_mode_vba_21.c845 *DestinationLinesForPrefetch = dml_min(*DestinationLinesForPrefetch, 63.75); in CalculatePrefetchSchedule()
1416 *dpte_row_height = dml_min(128, in CalculateVMAndRowBytes()
1428 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
1501 locals->PSCL_THROUGHPUT_LUMA[k] = dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1510 locals->PSCL_THROUGHPUT_LUMA[k] = dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1519 * dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1542 dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1552 locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1561 * dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1698 locals->SwathWidthY[k] = dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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Ddisplay_rq_dlg_calc_21.c110 * dml_min((double) recout_width, (double) hactive / 2.0) in get_refcyc_per_delivery()
610 dml_min( in get_meta_and_pte_attr()
736 vp_width = dml_min(full_src_vp_width, src_hactive_half); in get_surf_rq_param()
739 vp_height = dml_min(full_src_vp_width, src_hactive_half); in get_surf_rq_param()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c1494 max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit); in CalculateDCCConfiguration()
1495 max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit); in CalculateDCCConfiguration()
1874 …*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *… in CalculateVMAndRowBytes()
1882 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth); in CalculateVMAndRowBytes()
1971 v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1974 v->PSCL_THROUGHPUT_LUMA[k] = dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1980 * dml_max(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1996 v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1999 v->PSCL_THROUGHPUT_CHROMA[k] = dml_min( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2004 * dml_max3(v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]), in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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Ddisplay_rq_dlg_calc_30.c59 * dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2)) in get_refcyc_per_delivery()
793 vp_width = dml_min(full_src_vp_width, src_hactive_odm); in get_surf_rq_param()
796 vp_height = dml_min(full_src_vp_width, src_hactive_odm); in get_surf_rq_param()