Home
last modified time | relevance | path

Searched refs:dpll_md (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_crt.c95 u32 adpa, dpll_md; in cdv_intel_crt_mode_set() local
110 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
112 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); in cdv_intel_crt_mode_set()
Dpsb_drv.h242 u32 dpll_md; member
276 u32 dpll_md; member
Dcdv_device.c530 .dpll_md = DPLL_A_MD,
555 .dpll_md = DPLL_B_MD,
Dcdv_intel_display.c774 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U… in cdv_intel_crtc_mode_set()
/drivers/gpu/drm/i915/display/
Dintel_dpll.c865 u32 dpll_md = (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll() local
867 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
1125 pipe_config->dpll_hw_state.dpll_md = in vlv_compute_dpll()
1141 pipe_config->dpll_hw_state.dpll_md = in chv_compute_dpll()
1404 crtc_state->dpll_hw_state.dpll_md); in i9xx_enable_pll()
1480 pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1538 pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1540 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; in chv_enable_pll()
1551 pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
Dintel_dpll_mgr.h188 u32 dpll_md; member
Dintel_dpll_mgr.c555 hw_state->dpll_md, in ibx_dump_hw_state()
4347 hw_state->dpll_md, in intel_dpll_dump_hw_state()
Dintel_display_debugfs.c1109 pll->state.hw_state.dpll_md); in i915_shared_dplls_info()
Dintel_display.c4978 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
8520 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); in intel_pipe_config_compare()